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[PATCH v5 16/94] target/sparc: Merge gen_cond with only caller
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From: |
Richard Henderson |
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Subject: |
[PATCH v5 16/94] target/sparc: Merge gen_cond with only caller |
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Date: |
Sun, 22 Oct 2023 16:28:14 -0700 |
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/sparc/translate.c | 23 ++++++++---------------
1 file changed, 8 insertions(+), 15 deletions(-)
diff --git a/target/sparc/translate.c b/target/sparc/translate.c
index 69e85b1842..2664db302d 100644
--- a/target/sparc/translate.c
+++ b/target/sparc/translate.c
@@ -1309,20 +1309,6 @@ static void gen_fcompare(DisasCompare *cmp, unsigned int
cc, unsigned int cond)
}
}
-static void gen_cond(TCGv r_dst, unsigned int cc, unsigned int cond,
- DisasContext *dc)
-{
- DisasCompare cmp;
- gen_compare(&cmp, cc, cond, dc);
-
- /* The interface is to return a boolean in r_dst. */
- if (cmp.is_bool) {
- tcg_gen_mov_tl(r_dst, cmp.c1);
- } else {
- tcg_gen_setcond_tl(cmp.cond, r_dst, cmp.c1, cmp.c2);
- }
-}
-
static void gen_fcond(TCGv r_dst, unsigned int cc, unsigned int cond)
{
DisasCompare cmp;
@@ -2980,6 +2966,7 @@ static bool advance_jump_cond(DisasContext *dc, bool
annul, target_ulong dest)
static bool do_bpcc(DisasContext *dc, arg_bcc *a)
{
target_long target = address_mask_i(dc, dc->pc + a->i * 4);
+ DisasCompare cmp;
switch (a->cond) {
case 0x0:
@@ -2988,7 +2975,13 @@ static bool do_bpcc(DisasContext *dc, arg_bcc *a)
return advance_jump_uncond_always(dc, a->a, target);
default:
flush_cond(dc);
- gen_cond(cpu_cond, a->cc, a->cond, dc);
+
+ gen_compare(&cmp, a->cc, a->cond, dc);
+ if (cmp.is_bool) {
+ tcg_gen_mov_tl(cpu_cond, cmp.c1);
+ } else {
+ tcg_gen_setcond_tl(cmp.cond, cpu_cond, cmp.c1, cmp.c2);
+ }
return advance_jump_cond(dc, a->a, target);
}
}
--
2.34.1
- [PATCH v5 15/94] target/sparc: Move FBPfcc and FBfcc to decodetree, (continued)
- [PATCH v5 15/94] target/sparc: Move FBPfcc and FBfcc to decodetree, Richard Henderson, 2023/10/22
- [PATCH v5 18/94] target/sparc: Merge gen_branch_[an] with only caller, Richard Henderson, 2023/10/22
- [PATCH v5 26/94] target/sparc: Move WRASR to decodetree, Richard Henderson, 2023/10/22
- [PATCH v5 30/94] target/sparc: Remove cpu_wim, Richard Henderson, 2023/10/22
- [PATCH v5 32/94] target/sparc: Remove cpu_hintp, cpu_htba, cpu_hver, cpu_ssr, cpu_ver, Richard Henderson, 2023/10/22
- [PATCH v5 29/94] target/sparc: Move WRTBR, WRHPR to decodetree, Richard Henderson, 2023/10/22
- [PATCH v5 33/94] target/sparc: Move basic arithmetic to decodetree, Richard Henderson, 2023/10/22
- [PATCH v5 13/94] target/sparc: Move BPcc and Bicc to decodetree, Richard Henderson, 2023/10/22
- [PATCH v5 10/94] target/sparc: Add decodetree infrastructure, Richard Henderson, 2023/10/22
- [PATCH v5 34/94] target/sparc: Move ADDC to decodetree, Richard Henderson, 2023/10/22
- [PATCH v5 16/94] target/sparc: Merge gen_cond with only caller,
Richard Henderson <=
- [PATCH v5 20/94] target/sparc: Move SETHI to decodetree, Richard Henderson, 2023/10/22
- [PATCH v5 21/94] target/sparc: Move Tcc to decodetree, Richard Henderson, 2023/10/22
- [PATCH v5 19/94] target/sparc: Pass DisasCompare to advance_jump_cond, Richard Henderson, 2023/10/22
- [PATCH v5 24/94] target/sparc: Move RDWIM, RDPR to decodetree, Richard Henderson, 2023/10/22
- [PATCH v5 31/94] target/sparc: Remove cpu_tick_cmpr, cpu_stick_cmpr, cpu_hstick_cmpr, Richard Henderson, 2023/10/22
- [PATCH v5 36/94] target/sparc: Move UMUL, SMUL to decodetree, Richard Henderson, 2023/10/22
- [PATCH v5 38/94] target/sparc: Move UDIVX, SDIVX to decodetree, Richard Henderson, 2023/10/22
- [PATCH v5 23/94] target/sparc: Move RDPSR, RDHPR to decodetree, Richard Henderson, 2023/10/22
- [PATCH v5 27/94] target/sparc: Move WRPSR, SAVED, RESTORED to decodetree, Richard Henderson, 2023/10/22
- [PATCH v5 28/94] target/sparc: Move WRWIM, WRPR to decodetree, Richard Henderson, 2023/10/22