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[PATCH v5 16/20] hw/i386/pc: Support smp.clusters for x86 PC machine
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From: |
Zhao Liu |
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Subject: |
[PATCH v5 16/20] hw/i386/pc: Support smp.clusters for x86 PC machine |
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Date: |
Tue, 24 Oct 2023 17:03:19 +0800 |
From: Zhuocheng Ding <zhuocheng.ding@intel.com>
As module-level topology support is added to X86CPU, now we can enable
the support for the cluster parameter on PC machines. With this support,
we can define a 5-level x86 CPU topology with "-smp":
-smp cpus=*,maxcpus=*,sockets=*,dies=*,clusters=*,cores=*,threads=*.
Additionally, add the 5-level topology example in description of "-smp".
Signed-off-by: Zhuocheng Ding <zhuocheng.ding@intel.com>
Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
Reviewed-by: Yanan Wang <wangyanan55@huawei.com>
Tested-by: Babu Moger <babu.moger@amd.com>
Tested-by: Yongwei Ma <yongwei.ma@intel.com>
Acked-by: Michael S. Tsirkin <mst@redhat.com>
---
hw/i386/pc.c | 1 +
qemu-options.hx | 10 +++++-----
2 files changed, 6 insertions(+), 5 deletions(-)
diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index f7ee638becf4..e215913cafe3 100644
--- a/hw/i386/pc.c
+++ b/hw/i386/pc.c
@@ -1822,6 +1822,7 @@ static void pc_machine_class_init(ObjectClass *oc, void
*data)
mc->default_cpu_type = TARGET_DEFAULT_CPU_TYPE;
mc->nvdimm_supported = true;
mc->smp_props.dies_supported = true;
+ mc->smp_props.clusters_supported = true;
mc->default_ram_id = "pc.ram";
pcmc->default_smbios_ep_type = SMBIOS_ENTRY_POINT_TYPE_64;
diff --git a/qemu-options.hx b/qemu-options.hx
index e26230bac5f0..c65b77527b3c 100644
--- a/qemu-options.hx
+++ b/qemu-options.hx
@@ -337,14 +337,14 @@ SRST
-smp 8,sockets=2,cores=2,threads=2,maxcpus=8
The following sub-option defines a CPU topology hierarchy (2 sockets
- totally on the machine, 2 dies per socket, 2 cores per die, 2 threads
- per core) for PC machines which support sockets/dies/cores/threads.
- Some members of the option can be omitted but their values will be
- automatically computed:
+ totally on the machine, 2 dies per socket, 2 clusters per die, 2 cores per
+ cluster, 2 threads per core) for PC machines which support sockets/dies
+ /clusters/cores/threads. Some members of the option can be omitted but
+ their values will be automatically computed:
::
- -smp 16,sockets=2,dies=2,cores=2,threads=2,maxcpus=16
+ -smp 32,sockets=2,dies=2,clusters=2,cores=2,threads=2,maxcpus=32
The following sub-option defines a CPU topology hierarchy (2 sockets
totally on the machine, 2 clusters per socket, 2 cores per cluster,
--
2.34.1
- [PATCH v5 06/20] i386/cpu: Use APIC ID offset to encode cache topo in CPUID[4], (continued)
- [PATCH v5 06/20] i386/cpu: Use APIC ID offset to encode cache topo in CPUID[4], Zhao Liu, 2023/10/24
- [PATCH v5 07/20] i386/cpu: Consolidate the use of topo_info in cpu_x86_cpuid(), Zhao Liu, 2023/10/24
- [PATCH v5 08/20] i386: Split topology types of CPUID[0x1F] from the definitions of CPUID[0xB], Zhao Liu, 2023/10/24
- [PATCH v5 09/20] i386: Decouple CPUID[0x1F] subleaf with specific topology level, Zhao Liu, 2023/10/24
- [PATCH v5 10/20] i386: Introduce module-level cpu topology to CPUX86State, Zhao Liu, 2023/10/24
- [PATCH v5 12/20] i386: Expose module level in CPUID[0x1F], Zhao Liu, 2023/10/24
- [PATCH v5 11/20] i386: Support modules_per_die in X86CPUTopoInfo, Zhao Liu, 2023/10/24
- [PATCH v5 14/20] i386/cpu: Introduce cluster-id to X86CPU, Zhao Liu, 2023/10/24
- [PATCH v5 13/20] i386: Support module_id in X86CPUTopoIDs, Zhao Liu, 2023/10/24
- [PATCH v5 15/20] tests: Add test case of APIC ID for module level parsing, Zhao Liu, 2023/10/24
- [PATCH v5 16/20] hw/i386/pc: Support smp.clusters for x86 PC machine,
Zhao Liu <=
- [PATCH v5 17/20] i386: Add cache topology info in CPUCacheInfo, Zhao Liu, 2023/10/24
- [PATCH v5 19/20] i386: Use offsets get NumSharingCache for CPUID[0x8000001D].EAX[bits 25:14], Zhao Liu, 2023/10/24
- [PATCH v5 18/20] i386: Use CPUCacheInfo.share_level to encode CPUID[4], Zhao Liu, 2023/10/24
- [PATCH v5 20/20] i386: Use CPUCacheInfo.share_level to encode CPUID[0x8000001D].EAX[bits 25:14], Zhao Liu, 2023/10/24
- Re: [PATCH v5 00/20] Support smp.clusters for x86 in QEMU, Philippe Mathieu-Daudé, 2023/10/25