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[PULL 20/94] target/sparc: Move SETHI to decodetree
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From: |
Richard Henderson |
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Subject: |
[PULL 20/94] target/sparc: Move SETHI to decodetree |
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Date: |
Wed, 25 Oct 2023 17:14:18 -0700 |
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/sparc/insns.decode | 6 +++++
target/sparc/translate.c | 50 ++++++++++++---------------------------
2 files changed, 21 insertions(+), 35 deletions(-)
diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode
index 9ab3f2eb82..f6f5401b10 100644
--- a/target/sparc/insns.decode
+++ b/target/sparc/insns.decode
@@ -3,6 +3,10 @@
# Sparc instruction decode definitions.
# Copyright (c) 2023 Richard Henderson <rth@twiddle.net>
+##
+## Major Opcodes 00 and 01 -- branches, call, and sethi.
+##
+
&bcc i a cond cc
BPcc 00 a:1 cond:4 001 cc:1 0 - i:s19 &bcc
Bicc 00 a:1 cond:4 010 i:s22 &bcc cc=0
@@ -14,4 +18,6 @@ BPr 00 a:1 0 cond:3 011 .. - rs1:5 ..............
i=%d16
NCP 00 - ---- 111 ---------------------- # CBcc
+SETHI 00 rd:5 100 i:22
+
CALL 01 i:s30
diff --git a/target/sparc/translate.c b/target/sparc/translate.c
index d12f2b4b87..cdd929282a 100644
--- a/target/sparc/translate.c
+++ b/target/sparc/translate.c
@@ -2873,6 +2873,10 @@ static bool advance_pc(DisasContext *dc)
return true;
}
+/*
+ * Major opcodes 00 and 01 -- branches, call, and sethi
+ */
+
static bool advance_jump_uncond_never(DisasContext *dc, bool annul)
{
if (annul) {
@@ -3029,6 +3033,15 @@ static bool trans_NCP(DisasContext *dc, arg_NCP *a)
#endif
}
+static bool trans_SETHI(DisasContext *dc, arg_SETHI *a)
+{
+ /* Special-case %g0 because that's the canonical nop. */
+ if (a->rd) {
+ gen_store_gpr(dc, a->rd, tcg_constant_tl((uint32_t)a->i << 10));
+ }
+ return advance_pc(dc);
+}
+
#define CHECK_IU_FEATURE(dc, FEATURE) \
if (!((dc)->def->features & CPU_FEATURE_ ## FEATURE)) \
goto illegal_insn;
@@ -3049,41 +3062,8 @@ static void disas_sparc_legacy(DisasContext *dc,
unsigned int insn)
rd = GET_FIELD(insn, 2, 6);
switch (opc) {
- case 0: /* branches/sethi */
- {
- unsigned int xop = GET_FIELD(insn, 7, 9);
- switch (xop) {
-#ifdef TARGET_SPARC64
- case 0x1: /* V9 BPcc */
- g_assert_not_reached(); /* in decodetree */
- case 0x3: /* V9 BPr */
- g_assert_not_reached(); /* in decodetree */
- case 0x5: /* V9 FBPcc */
- g_assert_not_reached(); /* in decodetree */
-#else
- case 0x7: /* CBN+x */
- g_assert_not_reached(); /* in decodetree */
-#endif
- case 0x2: /* BN+x */
- g_assert_not_reached(); /* in decodetree */
- case 0x6: /* FBN+x */
- g_assert_not_reached(); /* in decodetree */
- case 0x4: /* SETHI */
- /* Special-case %g0 because that's the canonical nop. */
- if (rd) {
- uint32_t value = GET_FIELD(insn, 10, 31);
- TCGv t = gen_dest_gpr(dc, rd);
- tcg_gen_movi_tl(t, value << 10);
- gen_store_gpr(dc, rd, t);
- }
- break;
- case 0x0: /* UNIMPL */
- default:
- goto illegal_insn;
- }
- break;
- }
- break;
+ case 0:
+ goto illegal_insn; /* in decodetree */
case 1:
g_assert_not_reached(); /* in decodetree */
case 2: /* FPU & Logical Operations */
--
2.34.1
- [PATCH 15/29] tcg/mips: Support TCG_COND_TST{EQ,NE}, (continued)
- [PATCH 15/29] tcg/mips: Support TCG_COND_TST{EQ,NE}, Richard Henderson, 2023/10/25
- [PATCH 16/29] tcg/riscv: Support TCG_COND_TST{EQ,NE}, Richard Henderson, 2023/10/25
- [PULL 13/94] target/sparc: Move BPcc and Bicc to decodetree, Richard Henderson, 2023/10/25
- [PULL 11/94] target/sparc: Define AM_CHECK for sparc32, Richard Henderson, 2023/10/25
- [PULL 12/94] target/sparc: Move CALL to decodetree, Richard Henderson, 2023/10/25
- [PULL 06/94] target/sparc: Define features via cpu-feature.h.inc, Richard Henderson, 2023/10/25
- [PATCH 13/29] tcg/i386: Support TCG_COND_TST{EQ,NE}, Richard Henderson, 2023/10/25
- [PATCH 06/29] tcg/optimize: Handle TCG_COND_TST{EQ,NE}, Richard Henderson, 2023/10/25
- [PATCH 18/29] tcg/sparc64: Hoist read of tcg_cond_to_rcond, Richard Henderson, 2023/10/25
- [PULL 19/94] target/sparc: Pass DisasCompare to advance_jump_cond, Richard Henderson, 2023/10/25
- [PULL 20/94] target/sparc: Move SETHI to decodetree,
Richard Henderson <=
- [PULL 16/94] target/sparc: Merge gen_cond with only caller, Richard Henderson, 2023/10/25
- [PULL 17/94] target/sparc: Merge gen_fcond with only caller, Richard Henderson, 2023/10/25
- [PATCH 17/29] tcg/sparc64: Implement tcg_out_extrl_i64_i32, Richard Henderson, 2023/10/25
- [PULL 08/94] target/sparc: Remove sparcv7 cpu features, Richard Henderson, 2023/10/25
- [PULL 21/94] target/sparc: Move Tcc to decodetree, Richard Henderson, 2023/10/25
- [PATCH 22/29] tcg/ppc: Use cr0 in tcg_to_bc and tcg_to_isel, Richard Henderson, 2023/10/25
- [PATCH 23/29] tcg/ppc: Create tcg_out_and_rc, Richard Henderson, 2023/10/25
- [PULL 22/94] target/sparc: Move RDASR, STBAR, MEMBAR to decodetree, Richard Henderson, 2023/10/25
- [PULL 24/94] target/sparc: Move RDWIM, RDPR to decodetree, Richard Henderson, 2023/10/25
- [PATCH 21/29] tcg/ppc: Sink tcg_to_bc usage into tcg_out_bc, Richard Henderson, 2023/10/25