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[PATCH 20/29] tcg/sparc64: Support TCG_COND_TST{EQ,NE}
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From: |
Richard Henderson |
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Subject: |
[PATCH 20/29] tcg/sparc64: Support TCG_COND_TST{EQ,NE} |
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Date: |
Wed, 25 Oct 2023 17:14:19 -0700 |
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/sparc64/tcg-target.c.inc | 16 ++++++++++++++--
1 file changed, 14 insertions(+), 2 deletions(-)
diff --git a/tcg/sparc64/tcg-target.c.inc b/tcg/sparc64/tcg-target.c.inc
index e958e3c242..feeb318c39 100644
--- a/tcg/sparc64/tcg-target.c.inc
+++ b/tcg/sparc64/tcg-target.c.inc
@@ -606,9 +606,11 @@ static void tcg_out_div32(TCGContext *s, TCGReg rd, TCGReg
rs1,
uns ? ARITH_UDIV : ARITH_SDIV);
}
-static const uint8_t tcg_cond_to_bcond[] = {
+static const uint8_t tcg_cond_to_bcond[16] = {
[TCG_COND_EQ] = COND_E,
[TCG_COND_NE] = COND_NE,
+ [TCG_COND_TSTEQ] = COND_E,
+ [TCG_COND_TSTNE] = COND_NE,
[TCG_COND_LT] = COND_L,
[TCG_COND_GE] = COND_GE,
[TCG_COND_LE] = COND_LE,
@@ -648,7 +650,8 @@ static void tcg_out_bpcc(TCGContext *s, int scond, int
flags, TCGLabel *l)
static void tcg_out_cmp(TCGContext *s, TCGCond cond,
TCGReg c1, int32_t c2, int c2const)
{
- tcg_out_arithc(s, TCG_REG_G0, c1, c2, c2const, ARITH_SUBCC);
+ tcg_out_arithc(s, TCG_REG_G0, c1, c2, c2const,
+ is_tst_cond(cond) ? ARITH_ANDCC : ARITH_SUBCC);
}
static void tcg_out_brcond_i32(TCGContext *s, TCGCond cond, TCGReg arg1,
@@ -743,6 +746,15 @@ static void tcg_out_setcond_i32(TCGContext *s, TCGCond
cond, TCGReg ret,
cond = (cond == TCG_COND_EQ ? TCG_COND_GEU : TCG_COND_LTU);
break;
+ case TCG_COND_TSTEQ:
+ case TCG_COND_TSTNE:
+ /* Transform to inequality vs zero. */
+ tcg_out_arithc(s, TCG_REG_T1, c1, c2, c2const, ARITH_AND);
+ c1 = TCG_REG_G0;
+ c2 = TCG_REG_T1, c2const = 0;
+ cond = (cond == TCG_COND_TSTEQ ? TCG_COND_GEU : TCG_COND_LTU);
+ break;
+
case TCG_COND_GTU:
case TCG_COND_LEU:
/* If we don't need to load a constant into a register, we can
--
2.34.1
- [PULL 39/94] target/sparc: Move UDIV, SDIV to decodetree, (continued)
- [PULL 39/94] target/sparc: Move UDIV, SDIV to decodetree, Richard Henderson, 2023/10/25
- [PULL 43/94] target/sparc: Move POPC to decodetree, Richard Henderson, 2023/10/25
- [PULL 44/94] target/sparc: Convert remaining v8 coproc insns to decodetree, Richard Henderson, 2023/10/25
- [PULL 46/94] target/sparc: Move FLUSH, SAVE, RESTORE to decodetree, Richard Henderson, 2023/10/25
- [PULL 38/94] target/sparc: Move UDIVX, SDIVX to decodetree, Richard Henderson, 2023/10/25
- [PULL 47/94] target/sparc: Move DONE, RETRY to decodetree, Richard Henderson, 2023/10/25
- [PULL 50/94] target/sparc: Split out ldst functions with asi pre-computed, Richard Henderson, 2023/10/25
- [PULL 27/94] target/sparc: Move WRPSR, SAVED, RESTORED to decodetree, Richard Henderson, 2023/10/25
- [PULL 29/94] target/sparc: Move WRTBR, WRHPR to decodetree, Richard Henderson, 2023/10/25
- [PATCH 25/29] tcg/s390x: Support TCG_COND_TST{EQ,NE}, Richard Henderson, 2023/10/25
- [PATCH 20/29] tcg/sparc64: Support TCG_COND_TST{EQ,NE},
Richard Henderson <=
- [PATCH 27/29] target/alpha: Use TCG_COND_TST{EQ,NE} for BLB{C,S}, Richard Henderson, 2023/10/25
- [PULL 32/94] target/sparc: Remove cpu_hintp, cpu_htba, cpu_hver, cpu_ssr, cpu_ver, Richard Henderson, 2023/10/25
- [PULL 33/94] target/sparc: Move basic arithmetic to decodetree, Richard Henderson, 2023/10/25
- [PULL 40/94] target/sparc: Move TADD, TSUB, MULS to decodetree, Richard Henderson, 2023/10/25
- [PULL 45/94] target/sparc: Move JMPL, RETT, RETURN to decodetree, Richard Henderson, 2023/10/25
- [PULL 48/94] target/sparc: Split out resolve_asi, Richard Henderson, 2023/10/25
- [PULL 42/94] target/sparc: Move MOVcc, MOVR to decodetree, Richard Henderson, 2023/10/25
- [PULL 49/94] target/sparc: Drop ifdef around get_asi and friends, Richard Henderson, 2023/10/25
- [PULL 54/94] target/sparc: Move LDSTUB, LDSTUBA to decodetree, Richard Henderson, 2023/10/25
- [PULL 56/94] target/sparc: Move CASA, CASXA to decodetree, Richard Henderson, 2023/10/25