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[PATCH v2 18/35] tcg/riscv: Support TCG_COND_TST{EQ,NE}
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From: |
Richard Henderson |
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Subject: |
[PATCH v2 18/35] tcg/riscv: Support TCG_COND_TST{EQ,NE} |
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Date: |
Sat, 28 Oct 2023 12:45:05 -0700 |
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/riscv/tcg-target.c.inc | 20 ++++++++++++++++++--
1 file changed, 18 insertions(+), 2 deletions(-)
diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc
index 639363039b..358579b3fd 100644
--- a/tcg/riscv/tcg-target.c.inc
+++ b/tcg/riscv/tcg-target.c.inc
@@ -799,8 +799,14 @@ static const struct {
static void tcg_out_brcond(TCGContext *s, TCGCond cond, TCGReg arg1,
TCGReg arg2, TCGLabel *l)
{
- RISCVInsn op = tcg_brcond_to_riscv[cond].op;
+ RISCVInsn op;
+ if (is_tst_cond(cond)) {
+ tcg_out_opc_reg(s, OPC_AND, TCG_REG_TMP0, arg1, arg2);
+ cond = tcg_tst_eqne_cond(cond);
+ }
+
+ op = tcg_brcond_to_riscv[cond].op;
tcg_debug_assert(op != 0);
if (tcg_brcond_to_riscv[cond].swap) {
@@ -828,6 +834,7 @@ static int tcg_out_setcond_int(TCGContext *s, TCGCond cond,
TCGReg ret,
case TCG_COND_GEU: /* -> LTU */
case TCG_COND_GT: /* -> LE */
case TCG_COND_GTU: /* -> LEU */
+ case TCG_COND_TSTEQ: /* -> TSTNE */
cond = tcg_invert_cond(cond);
flags ^= SETCOND_INV;
break;
@@ -887,6 +894,15 @@ static int tcg_out_setcond_int(TCGContext *s, TCGCond
cond, TCGReg ret,
}
break;
+ case TCG_COND_TSTNE:
+ flags |= SETCOND_NEZ;
+ if (c2) {
+ tcg_out_opc_imm(s, OPC_ANDI, ret, arg1, arg2);
+ } else {
+ tcg_out_opc_reg(s, OPC_AND, ret, arg1, arg2);
+ }
+ break;
+
case TCG_COND_LT:
if (c2) {
tcg_out_opc_imm(s, OPC_SLTI, ret, arg1, arg2);
@@ -1080,7 +1096,7 @@ static void tcg_out_movcond(TCGContext *s, TCGCond cond,
TCGReg ret,
int tmpflags;
TCGReg t;
- if (!have_zicond && (!c_cmp2 || cmp2 == 0)) {
+ if (!have_zicond && (!c_cmp2 || cmp2 == 0) && !is_tst_cond(cond)) {
tcg_out_movcond_br2(s, cond, ret, cmp1, cmp2,
val1, c_val1, val2, c_val2);
return;
--
2.34.1
- [PATCH v2 09/35] tcg/aarch64: Generate TBZ, TBNZ, (continued)
- [PATCH v2 09/35] tcg/aarch64: Generate TBZ, TBNZ, Richard Henderson, 2023/10/28
- [PATCH v2 08/35] tcg/aarch64: Support TCG_COND_TST{EQ,NE}, Richard Henderson, 2023/10/28
- [PATCH v2 10/35] tcg/aarch64: Generate CBNZ for TSTNE of UINT32_MAX, Richard Henderson, 2023/10/28
- [PATCH v2 06/35] tcg/optimize: Handle TCG_COND_TST{EQ,NE}, Richard Henderson, 2023/10/28
- [PATCH v2 24/35] tcg/ppc: Use cr0 in tcg_to_bc and tcg_to_isel, Richard Henderson, 2023/10/28
- [PATCH v2 16/35] tcg/loongarch64: Support TCG_COND_TST{EQ,NE}, Richard Henderson, 2023/10/28
- [PATCH v2 11/35] tcg/arm: Support TCG_COND_TST{EQ,NE}, Richard Henderson, 2023/10/28
- [PATCH v2 26/35] tcg/ppc: Add TCG_CT_CONST_CMP, Richard Henderson, 2023/10/28
- [PATCH v2 14/35] tcg/i386: Support TCG_COND_TST{EQ,NE}, Richard Henderson, 2023/10/28
- [PATCH v2 15/35] tcg/i386: Improve TSTNE/TESTEQ vs powers of two, Richard Henderson, 2023/10/28
- [PATCH v2 18/35] tcg/riscv: Support TCG_COND_TST{EQ,NE},
Richard Henderson <=
- [PATCH v2 21/35] tcg/sparc64: Pass TCGCond to tcg_out_cmp, Richard Henderson, 2023/10/28
- [PATCH v2 25/35] tcg/ppc: Tidy up tcg_target_const_match, Richard Henderson, 2023/10/28
- [PATCH v2 28/35] tcg/s390x: Split constraint A into J+U, Richard Henderson, 2023/10/28
- [PATCH v2 32/35] target/alpha: Use TCG_COND_TST{EQ,NE} for BLB{C,S}, Richard Henderson, 2023/10/28
- [PATCH v2 33/35] target/alpha: Use TCG_COND_TST{EQ, NE} for CMOVLB{C, S}, Richard Henderson, 2023/10/28
- [PATCH v2 12/35] tcg/i386: Pass x86 condition codes to tcg_out_cmov, Richard Henderson, 2023/10/28
- [PATCH v2 13/35] tcg/i386: Move tcg_cond_to_jcc[] into tcg_out_cmp, Richard Henderson, 2023/10/28
- [PATCH v2 20/35] tcg/sparc64: Hoist read of tcg_cond_to_rcond, Richard Henderson, 2023/10/28
- [PATCH v2 23/35] tcg/ppc: Sink tcg_to_bc usage into tcg_out_bc, Richard Henderson, 2023/10/28
- [PATCH v2 17/35] tcg/mips: Support TCG_COND_TST{EQ,NE}, Richard Henderson, 2023/10/28