Re: [PATCH 2/3] target/riscv: Don't adjust vscause for exceptions

[Daniel Henrique Barboza]

On 1/7/24 21:13, Alistair Francis wrote:
> We have been incorrectly adjusting both the interrupt and exception
> cause when using the hypervisor extension and trapping to VS-mode. This
> patch changes the conditional to ensure we only adjust the cause for
> interrupts and not exceptions.
>
> Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1708
> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> ---

Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

>   target/riscv/cpu_helper.c | 4 ++--
>   1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
> index e7e23b34f4..886a558a42 100644
> --- a/target/riscv/cpu_helper.c
> +++ b/target/riscv/cpu_helper.c
> @@ -1749,8 +1749,8 @@ void riscv_cpu_do_interrupt(CPUState *cs)
>                    * See if we need to adjust cause. Yes if its VS mode 
> interrupt
>                    * no if hypervisor has delegated one of hs mode's interrupt
>                    */
> -                if (cause == IRQ_VS_TIMER || cause == IRQ_VS_SOFT ||
> -                    cause == IRQ_VS_EXT) {
> +                if (async && (cause == IRQ_VS_TIMER || cause == IRQ_VS_SOFT ||
> +                              cause == IRQ_VS_EXT)) {
>                       cause = cause - 1;
>                   }
>                   write_gva = false;