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[PULL 01/65] target/riscv: Add vill check for whole vector register move
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From: |
Alistair Francis |
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Subject: |
[PULL 01/65] target/riscv: Add vill check for whole vector register move instructions |
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Date: |
Wed, 10 Jan 2024 18:56:29 +1000 |
From: Max Chou <max.chou@sifive.com>
The ratified version of RISC-V V spec section 16.6 says that
`The instructions operate as if EEW=SEW`.
So the whole vector register move instructions depend on the vtype
register that means the whole vector register move instructions should
raise an illegal-instruction exception when vtype.vill=1.
Signed-off-by: Max Chou <max.chou@sifive.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20231129170400.21251-2-max.chou@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/insn_trans/trans_rvv.c.inc | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc
b/target/riscv/insn_trans/trans_rvv.c.inc
index 78bd363310..114ad87397 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -3631,13 +3631,14 @@ static bool trans_vcompress_vm(DisasContext *s, arg_r
*a)
}
/*
- * Whole Vector Register Move Instructions ignore vtype and vl setting.
- * Thus, we don't need to check vill bit. (Section 16.6)
+ * Whole Vector Register Move Instructions depend on vtype register(vsew).
+ * Thus, we need to check vill bit. (Section 16.6)
*/
#define GEN_VMV_WHOLE_TRANS(NAME, LEN) \
static bool trans_##NAME(DisasContext *s, arg_##NAME * a) \
{ \
if (require_rvv(s) && \
+ vext_check_isa_ill(s) && \
QEMU_IS_ALIGNED(a->rd, LEN) && \
QEMU_IS_ALIGNED(a->rs2, LEN)) { \
uint32_t maxsz = (s->cfg_ptr->vlen >> 3) * LEN; \
--
2.43.0
- [PULL 00/65] riscv-to-apply queue, Alistair Francis, 2024/01/10
- [PULL 01/65] target/riscv: Add vill check for whole vector register move instructions,
Alistair Francis <=
- [PULL 03/65] target/riscv: Fix th.dcache.cval1 priviledge check, Alistair Francis, 2024/01/10
- [PULL 02/65] target/riscv: The whole vector register move instructions depend on vsew, Alistair Francis, 2024/01/10
- [PULL 04/65] target/riscv: Not allow write mstatus_vs without RVV, Alistair Francis, 2024/01/10
- [PULL 05/65] target/riscv/pmp: Use hwaddr instead of target_ulong for RV32, Alistair Francis, 2024/01/10
- [PULL 06/65] target/riscv/cpu.c: fix machine IDs getters, Alistair Francis, 2024/01/10
- [PULL 07/65] target/riscv/kvm: change KVM_REG_RISCV_FP_F to u32, Alistair Francis, 2024/01/10
- [PULL 08/65] target/riscv/kvm: change KVM_REG_RISCV_FP_D to u64, Alistair Francis, 2024/01/10
- [PULL 09/65] target/riscv/kvm: change timer regs size to u64, Alistair Francis, 2024/01/10
- [PULL 11/65] target/riscv/kvm: rename riscv_reg_id() to riscv_reg_id_ulong(), Alistair Francis, 2024/01/10
- [PULL 12/65] hw/arm/virt-acpi-build.c: Migrate fw_cfg creation to common location, Alistair Francis, 2024/01/10