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[PULL 64/65] target/riscv: Don't adjust vscause for exceptions
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From: |
Alistair Francis |
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Subject: |
[PULL 64/65] target/riscv: Don't adjust vscause for exceptions |
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Date: |
Wed, 10 Jan 2024 18:57:32 +1000 |
From: Alistair Francis <alistair23@gmail.com>
We have been incorrectly adjusting both the interrupt and exception
cause when using the hypervisor extension and trapping to VS-mode. This
patch changes the conditional to ensure we only adjust the cause for
interrupts and not exceptions.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1708
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20240108001328.280222-3-alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu_helper.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 99d1275729..c7cc7eb423 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -1749,8 +1749,8 @@ void riscv_cpu_do_interrupt(CPUState *cs)
* See if we need to adjust cause. Yes if its VS mode interrupt
* no if hypervisor has delegated one of hs mode's interrupt
*/
- if (cause == IRQ_VS_TIMER || cause == IRQ_VS_SOFT ||
- cause == IRQ_VS_EXT) {
+ if (async && (cause == IRQ_VS_TIMER || cause == IRQ_VS_SOFT ||
+ cause == IRQ_VS_EXT)) {
cause = cause - 1;
}
write_gva = false;
--
2.43.0
- [PULL 55/65] target/riscv/kvm.c: remove group setting of KVM AIA if the machine only has 1 socket, (continued)
- [PULL 55/65] target/riscv/kvm.c: remove group setting of KVM AIA if the machine only has 1 socket, Alistair Francis, 2024/01/10
- [PULL 56/65] linux-headers: Update to Linux v6.7-rc5, Alistair Francis, 2024/01/10
- [PULL 57/65] linux-headers: riscv: add ptrace.h, Alistair Francis, 2024/01/10
- [PULL 63/65] target/riscv: Assert that the CSR numbers will be correct, Alistair Francis, 2024/01/10
- [PULL 61/65] roms/opensbi: Upgrade from v1.3.1 to v1.4, Alistair Francis, 2024/01/10
- [PULL 62/65] target/riscv: pmp: Ignore writes when RW=01 and MML=0, Alistair Francis, 2024/01/10
- [PULL 58/65] target/riscv/kvm: do PR_RISCV_V_SET_CONTROL during realize(), Alistair Francis, 2024/01/10
- [PULL 59/65] target/riscv/kvm: add RVV and Vector CSR regs, Alistair Francis, 2024/01/10
- [PULL 60/65] docs/system/riscv: sifive_u: Update S-mode U-Boot image build instructions, Alistair Francis, 2024/01/10
- [PULL 65/65] target/riscv: Ensure mideleg is set correctly on reset, Alistair Francis, 2024/01/10
- [PULL 64/65] target/riscv: Don't adjust vscause for exceptions,
Alistair Francis <=
- Re: [PULL 00/65] riscv-to-apply queue, Peter Maydell, 2024/01/10