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[PULL 07/41] hw/arm: Add missing QOM parent for v7-M SoCs
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From: |
Peter Maydell |
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Subject: |
[PULL 07/41] hw/arm: Add missing QOM parent for v7-M SoCs |
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Date: |
Thu, 11 Jan 2024 11:04:31 +0000 |
From: Philippe Mathieu-Daudé <philmd@linaro.org>
QDev objects created with qdev_new() need to manually add
their parent relationship with object_property_add_child().
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20240104141159.53883-1-philmd@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/arm/msf2-som.c | 1 +
hw/arm/netduino2.c | 1 +
hw/arm/netduinoplus2.c | 1 +
hw/arm/olimex-stm32-h405.c | 1 +
hw/arm/stm32vldiscovery.c | 1 +
5 files changed, 5 insertions(+)
diff --git a/hw/arm/msf2-som.c b/hw/arm/msf2-som.c
index eb74b23797c..a269cf044b9 100644
--- a/hw/arm/msf2-som.c
+++ b/hw/arm/msf2-som.c
@@ -60,6 +60,7 @@ static void emcraft_sf2_s2s010_init(MachineState *machine)
memory_region_add_subregion(sysmem, DDR_BASE_ADDRESS, ddr);
dev = qdev_new(TYPE_MSF2_SOC);
+ object_property_add_child(OBJECT(machine), "soc", OBJECT(dev));
qdev_prop_set_string(dev, "part-name", "M2S010");
qdev_prop_set_string(dev, "cpu-type", mc->default_cpu_type);
diff --git a/hw/arm/netduino2.c b/hw/arm/netduino2.c
index 501f63a77f9..8b1a9a24379 100644
--- a/hw/arm/netduino2.c
+++ b/hw/arm/netduino2.c
@@ -44,6 +44,7 @@ static void netduino2_init(MachineState *machine)
clock_set_hz(sysclk, SYSCLK_FRQ);
dev = qdev_new(TYPE_STM32F205_SOC);
+ object_property_add_child(OBJECT(machine), "soc", OBJECT(dev));
qdev_connect_clock_in(dev, "sysclk", sysclk);
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
diff --git a/hw/arm/netduinoplus2.c b/hw/arm/netduinoplus2.c
index 2e589849478..bccd1003549 100644
--- a/hw/arm/netduinoplus2.c
+++ b/hw/arm/netduinoplus2.c
@@ -44,6 +44,7 @@ static void netduinoplus2_init(MachineState *machine)
clock_set_hz(sysclk, SYSCLK_FRQ);
dev = qdev_new(TYPE_STM32F405_SOC);
+ object_property_add_child(OBJECT(machine), "soc", OBJECT(dev));
qdev_connect_clock_in(dev, "sysclk", sysclk);
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
diff --git a/hw/arm/olimex-stm32-h405.c b/hw/arm/olimex-stm32-h405.c
index d793de7c97f..4ad7b043be0 100644
--- a/hw/arm/olimex-stm32-h405.c
+++ b/hw/arm/olimex-stm32-h405.c
@@ -47,6 +47,7 @@ static void olimex_stm32_h405_init(MachineState *machine)
clock_set_hz(sysclk, SYSCLK_FRQ);
dev = qdev_new(TYPE_STM32F405_SOC);
+ object_property_add_child(OBJECT(machine), "soc", OBJECT(dev));
qdev_connect_clock_in(dev, "sysclk", sysclk);
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
diff --git a/hw/arm/stm32vldiscovery.c b/hw/arm/stm32vldiscovery.c
index 190db6118b9..cc419351605 100644
--- a/hw/arm/stm32vldiscovery.c
+++ b/hw/arm/stm32vldiscovery.c
@@ -47,6 +47,7 @@ static void stm32vldiscovery_init(MachineState *machine)
clock_set_hz(sysclk, SYSCLK_FRQ);
dev = qdev_new(TYPE_STM32F100_SOC);
+ object_property_add_child(OBJECT(machine), "soc", OBJECT(dev));
qdev_connect_clock_in(dev, "sysclk", sysclk);
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
--
2.34.1
- [PULL 00/41] target-arm queue, Peter Maydell, 2024/01/11
- [PULL 01/41] hw/arm: add cache controller for Freescale i.MX6, Peter Maydell, 2024/01/11
- [PULL 04/41] hw/intc/armv7m_nvic: add "num-prio-bits" property, Peter Maydell, 2024/01/11
- [PULL 07/41] hw/arm: Add missing QOM parent for v7-M SoCs,
Peter Maydell <=
- [PULL 03/41] hw/arm: Add minimal support for the B-L475E-IOT01A board, Peter Maydell, 2024/01/11
- [PULL 05/41] hw/arm/armv7m: alias the NVIC "num-prio-bits" property, Peter Maydell, 2024/01/11
- [PULL 14/41] target/arm: Allow use of upper 32 bits of TBFLAG_A64, Peter Maydell, 2024/01/11
- [PULL 41/41] target/arm: Add FEAT_NV2 to max, neoverse-n2, neoverse-v1 CPUs, Peter Maydell, 2024/01/11
- [PULL 38/41] hw/intc/arm_gicv3_cpuif: Mark up VNCR offsets for GIC CPU registers, Peter Maydell, 2024/01/11
- [PULL 02/41] hw/arm: Add minimal support for the STM32L4x5 SoC, Peter Maydell, 2024/01/11
- [PULL 06/41] hw/arm/socs: configure priority bits for existing SOCs, Peter Maydell, 2024/01/11
- [PULL 09/41] hw/intc/arm_gicv3_cpuif: handle LPIs in in the list registers, Peter Maydell, 2024/01/11
- [PULL 08/41] target/arm: Set CTR_EL0.{IDC,DIC} for the 'max' CPU, Peter Maydell, 2024/01/11