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[PULL 20/21] hw/arm/virt: Consolidate valid CPU types
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From: |
Peter Maydell |
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Subject: |
[PULL 20/21] hw/arm/virt: Consolidate valid CPU types |
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Date: |
Tue, 16 Jan 2024 15:12:27 +0000 |
From: Gavin Shan <gshan@redhat.com>
It's found that some of the CPU type names in the array of valid
CPU types are invalid because their corresponding classes aren't
registered, as reported by Peter Maydell.
[gshan@gshan build]$ ./qemu-system-arm -machine virt -cpu cortex-a9
qemu-system-arm: Invalid CPU model: cortex-a9
The valid models are: cortex-a7, cortex-a15, (null), (null), (null),
(null), (null), (null), (null), (null), (null), (null), (null), max
Fix it by consolidating the array of valid CPU types. After it's
applied, we have the following output when TCG is enabled.
[gshan@gshan build]$ ./qemu-system-arm -machine virt -cpu cortex-a9
qemu-system-arm: Invalid CPU model: cortex-a9
The valid models are: cortex-a7, cortex-a15, max
[gshan@gshan build]$ ./qemu-system-aarch64 -machine virt -cpu cortex-a9
qemu-system-aarch64: Invalid CPU model: cortex-a9
The valid models are: cortex-a7, cortex-a15, cortex-a35, cortex-a55,
cortex-a72, cortex-a76, cortex-a710, a64fx, neoverse-n1, neoverse-v1,
neoverse-n2, cortex-a53, cortex-a57, max
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2084
Reported-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Gavin Shan <gshan@redhat.com>
Reviewed-by: Cornelia Huck <cohuck@redhat.com>
Message-id: 20240111051054.83304-1-gshan@redhat.com
Fixes: fa8c617791 ("hw/arm/virt: Check CPU type in machine_run_board_init()")
Signed-off-by: Gavin Shan <gshan@redhat.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/arm/virt.c | 8 ++++++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index 2793121cb41..5cbc69dff83 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -2905,6 +2905,7 @@ static void virt_machine_class_init(ObjectClass *oc, void
*data)
#ifdef CONFIG_TCG
ARM_CPU_TYPE_NAME("cortex-a7"),
ARM_CPU_TYPE_NAME("cortex-a15"),
+#ifdef TARGET_AARCH64
ARM_CPU_TYPE_NAME("cortex-a35"),
ARM_CPU_TYPE_NAME("cortex-a55"),
ARM_CPU_TYPE_NAME("cortex-a72"),
@@ -2914,12 +2915,15 @@ static void virt_machine_class_init(ObjectClass *oc,
void *data)
ARM_CPU_TYPE_NAME("neoverse-n1"),
ARM_CPU_TYPE_NAME("neoverse-v1"),
ARM_CPU_TYPE_NAME("neoverse-n2"),
-#endif
+#endif /* TARGET_AARCH64 */
+#endif /* CONFIG_TCG */
+#ifdef TARGET_AARCH64
ARM_CPU_TYPE_NAME("cortex-a53"),
ARM_CPU_TYPE_NAME("cortex-a57"),
#if defined(CONFIG_KVM) || defined(CONFIG_HVF)
ARM_CPU_TYPE_NAME("host"),
-#endif
+#endif /* CONFIG_KVM || CONFIG_HVF */
+#endif /* TARGET_AARCH64 */
ARM_CPU_TYPE_NAME("max"),
NULL
};
--
2.34.1
- [PULL 18/21] tests/qtest: Adding PCS Module test to GMAC Qtest, (continued)
- [PULL 18/21] tests/qtest: Adding PCS Module test to GMAC Qtest, Peter Maydell, 2024/01/16
- [PULL 19/21] hw/timer: fix systick trace message, Peter Maydell, 2024/01/16
- [PULL 10/21] hw/misc: Add Nuvoton's PCI Mailbox Module, Peter Maydell, 2024/01/16
- [PULL 14/21] hw/arm: Add GMAC devices to NPCM7XX SoC, Peter Maydell, 2024/01/16
- [PULL 13/21] hw/net: Add NPCMXXX GMAC device, Peter Maydell, 2024/01/16
- [PULL 11/21] hw/arm: Add PCI mailbox module to Nuvoton SoC, Peter Maydell, 2024/01/16
- [PULL 15/21] tests/qtest: Creating qtest for GMAC Module, Peter Maydell, 2024/01/16
- [PULL 16/21] hw/net: GMAC Rx Implementation, Peter Maydell, 2024/01/16
- [PULL 17/21] hw/net: GMAC Tx Implementation, Peter Maydell, 2024/01/16
- [PULL 21/21] load_elf: fix iterator's type for elf file processing, Peter Maydell, 2024/01/16
- [PULL 20/21] hw/arm/virt: Consolidate valid CPU types,
Peter Maydell <=