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Re: [PATCH 4/5] hw/cxl: Update mailbox status registers.
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From: |
fan |
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Subject: |
Re: [PATCH 4/5] hw/cxl: Update mailbox status registers. |
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Date: |
Wed, 24 Jan 2024 10:57:00 -0800 |
On Wed, Jan 24, 2024 at 01:48:13PM +0000, Jonathan Cameron wrote:
> Whilst the reported version was 1 so there should be no changes,
> a couple of fields (where the value 0 was valid) were not
> defined. Make those explicit and update references to be based
> on CXL r3.1.
>
> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Fan Ni <fan.ni@samsung.com>
> ---
> include/hw/cxl/cxl_device.h | 17 ++++++++++-------
> hw/cxl/cxl-device-utils.c | 6 +++++-
> 2 files changed, 15 insertions(+), 8 deletions(-)
>
> diff --git a/include/hw/cxl/cxl_device.h b/include/hw/cxl/cxl_device.h
> index 31d2afcd3d..9f51c586d7 100644
> --- a/include/hw/cxl/cxl_device.h
> +++ b/include/hw/cxl/cxl_device.h
> @@ -189,7 +189,7 @@ typedef struct cxl_device_state {
> };
> };
>
> - /* mmio for the mailbox registers 8.2.8.4 */
> + /* CXL r3.1 Section 8.2.8.4: Mailbox Registers */
> struct {
> MemoryRegion mailbox;
> uint16_t payload_size;
> @@ -310,39 +310,42 @@ void cxl_initialize_t3_ld_cci(CXLCCI *cci, DeviceState
> *d,
> REG64(CXL_DEV_EVENT_STATUS, 0)
> FIELD(CXL_DEV_EVENT_STATUS, EVENT_STATUS, 0, 32)
>
> -/* CXL 2.0 8.2.8.4.3 Mailbox Capabilities Register */
> +#define CXL_DEV_MAILBOX_VERSION 1
> +/* CXL r3.1 Section 8.2.8.4.3: Mailbox Capabilities Register */
> REG32(CXL_DEV_MAILBOX_CAP, 0)
> FIELD(CXL_DEV_MAILBOX_CAP, PAYLOAD_SIZE, 0, 5)
> FIELD(CXL_DEV_MAILBOX_CAP, INT_CAP, 5, 1)
> FIELD(CXL_DEV_MAILBOX_CAP, BG_INT_CAP, 6, 1)
> FIELD(CXL_DEV_MAILBOX_CAP, MSI_N, 7, 4)
> + FIELD(CXL_DEV_MAILBOX_CAP, MBOX_READY_TIME, 11, 8)
> + FIELD(CXL_DEV_MAILBOX_CAP, TYPE, 19, 4)
>
> -/* CXL 2.0 8.2.8.4.4 Mailbox Control Register */
> +/* CXL r3.1 Section 8.2.8.4.4: Mailbox Control Register */
> REG32(CXL_DEV_MAILBOX_CTRL, 4)
> FIELD(CXL_DEV_MAILBOX_CTRL, DOORBELL, 0, 1)
> FIELD(CXL_DEV_MAILBOX_CTRL, INT_EN, 1, 1)
> FIELD(CXL_DEV_MAILBOX_CTRL, BG_INT_EN, 2, 1)
>
> -/* CXL 2.0 8.2.8.4.5 Command Register */
> +/* CXL r3.1 Section 8.2.8.4.5: Command Register */
> REG64(CXL_DEV_MAILBOX_CMD, 8)
> FIELD(CXL_DEV_MAILBOX_CMD, COMMAND, 0, 8)
> FIELD(CXL_DEV_MAILBOX_CMD, COMMAND_SET, 8, 8)
> FIELD(CXL_DEV_MAILBOX_CMD, LENGTH, 16, 20)
>
> -/* CXL 2.0 8.2.8.4.6 Mailbox Status Register */
> +/* CXL r3.1 Section 8.2.8.4.6: Mailbox Status Register */
> REG64(CXL_DEV_MAILBOX_STS, 0x10)
> FIELD(CXL_DEV_MAILBOX_STS, BG_OP, 0, 1)
> FIELD(CXL_DEV_MAILBOX_STS, ERRNO, 32, 16)
> FIELD(CXL_DEV_MAILBOX_STS, VENDOR_ERRNO, 48, 16)
>
> -/* CXL 2.0 8.2.8.4.7 Background Command Status Register */
> +/* CXL r3.1 Section 8.2.8.4.7: Background Command Status Register */
> REG64(CXL_DEV_BG_CMD_STS, 0x18)
> FIELD(CXL_DEV_BG_CMD_STS, OP, 0, 16)
> FIELD(CXL_DEV_BG_CMD_STS, PERCENTAGE_COMP, 16, 7)
> FIELD(CXL_DEV_BG_CMD_STS, RET_CODE, 32, 16)
> FIELD(CXL_DEV_BG_CMD_STS, VENDOR_RET_CODE, 48, 16)
>
> -/* CXL 2.0 8.2.8.4.8 Command Payload Registers */
> +/* CXL r3.1 Section 8.2.8.4.8: Command Payload Registers */
> REG32(CXL_DEV_CMD_PAYLOAD, 0x20)
>
> REG64(CXL_MEM_DEV_STS, 0)
> diff --git a/hw/cxl/cxl-device-utils.c b/hw/cxl/cxl-device-utils.c
> index 40b619ffd9..9df8738f86 100644
> --- a/hw/cxl/cxl-device-utils.c
> +++ b/hw/cxl/cxl-device-utils.c
> @@ -366,6 +366,10 @@ static void mailbox_reg_init_common(CXLDeviceState
> *cxl_dstate)
> ARRAY_FIELD_DP32(cxl_dstate->mbox_reg_state32, CXL_DEV_MAILBOX_CAP,
> MSI_N, msi_n);
> cxl_dstate->mbox_msi_n = msi_n;
> + ARRAY_FIELD_DP32(cxl_dstate->mbox_reg_state32, CXL_DEV_MAILBOX_CAP,
> + MBOX_READY_TIME, 0); /* Not reported */
> + ARRAY_FIELD_DP32(cxl_dstate->mbox_reg_state32, CXL_DEV_MAILBOX_CAP,
> + TYPE, 0); /* Inferred from class code */
> }
>
> static void memdev_reg_init_common(CXLDeviceState *cxl_dstate)
> @@ -392,7 +396,7 @@ void cxl_device_register_init_t3(CXLType3Dev *ct3d)
> cxl_device_cap_init(cxl_dstate, DEVICE_STATUS, 1, 2);
> device_reg_init_common(cxl_dstate);
>
> - cxl_device_cap_init(cxl_dstate, MAILBOX, 2, 1);
> + cxl_device_cap_init(cxl_dstate, MAILBOX, 2, CXL_DEV_MAILBOX_VERSION);
> mailbox_reg_init_common(cxl_dstate);
>
> cxl_device_cap_init(cxl_dstate, MEMORY_DEVICE, 0x4000, 1);
> --
> 2.39.2
>
- [PATCH 0/5 qemu] hw/cxl: Update CXL emulation to reflect and reference r3.1, Jonathan Cameron, 2024/01/24
- [PATCH 1/5] hw/cxl: Update HDM Decoder capability to version 3, Jonathan Cameron, 2024/01/24
- [PATCH 2/5] hw/cxl: Update link register definitions., Jonathan Cameron, 2024/01/24
- [PATCH 3/5] hw/cxl: Update RAS Capability Definitions for version 3., Jonathan Cameron, 2024/01/24
- [PATCH 4/5] hw/cxl: Update mailbox status registers., Jonathan Cameron, 2024/01/24
- Re: [PATCH 4/5] hw/cxl: Update mailbox status registers.,
fan <=
- [PATCH 5/5] hw/cxl: Standardize all references on CXL r3.1 and minor updates, Jonathan Cameron, 2024/01/24