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[PATCH 07/33] target/cris: Cache mem_index in DisasContext
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From: |
Richard Henderson |
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Subject: |
[PATCH 07/33] target/cris: Cache mem_index in DisasContext |
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Date: |
Tue, 30 Jan 2024 09:30:17 +1000 |
Compute this value once for each translation.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/cris/translate.c | 14 +++++---------
target/cris/translate_v10.c.inc | 6 ++----
2 files changed, 7 insertions(+), 13 deletions(-)
diff --git a/target/cris/translate.c b/target/cris/translate.c
index ee1402a9a3..7acea29a01 100644
--- a/target/cris/translate.c
+++ b/target/cris/translate.c
@@ -94,6 +94,7 @@ typedef struct DisasContext {
CRISCPU *cpu;
target_ulong pc, ppc;
+ int mem_index;
/* Decoder. */
unsigned int (*decoder)(CPUCRISState *env, struct DisasContext *dc);
@@ -1008,37 +1009,31 @@ static inline void cris_prepare_jmp (DisasContext *dc,
unsigned int type)
static void gen_load64(DisasContext *dc, TCGv_i64 dst, TCGv addr)
{
- int mem_index = cpu_mmu_index(&dc->cpu->env, false);
-
/* If we get a fault on a delayslot we must keep the jmp state in
the cpu-state to be able to re-execute the jmp. */
if (dc->delayed_branch == 1) {
cris_store_direct_jmp(dc);
}
- tcg_gen_qemu_ld_i64(dst, addr, mem_index, MO_TEUQ);
+ tcg_gen_qemu_ld_i64(dst, addr, dc->mem_index, MO_TEUQ);
}
static void gen_load(DisasContext *dc, TCGv dst, TCGv addr,
unsigned int size, int sign)
{
- int mem_index = cpu_mmu_index(&dc->cpu->env, false);
-
/* If we get a fault on a delayslot we must keep the jmp state in
the cpu-state to be able to re-execute the jmp. */
if (dc->delayed_branch == 1) {
cris_store_direct_jmp(dc);
}
- tcg_gen_qemu_ld_tl(dst, addr, mem_index,
+ tcg_gen_qemu_ld_tl(dst, addr, dc->mem_index,
MO_TE + ctz32(size) + (sign ? MO_SIGN : 0));
}
static void gen_store (DisasContext *dc, TCGv addr, TCGv val,
unsigned int size)
{
- int mem_index = cpu_mmu_index(&dc->cpu->env, false);
-
/* If we get a fault on a delayslot we must keep the jmp state in
the cpu-state to be able to re-execute the jmp. */
if (dc->delayed_branch == 1) {
@@ -1055,7 +1050,7 @@ static void gen_store (DisasContext *dc, TCGv addr, TCGv
val,
return;
}
- tcg_gen_qemu_st_tl(val, addr, mem_index, MO_TE + ctz32(size));
+ tcg_gen_qemu_st_tl(val, addr, dc->mem_index, MO_TE + ctz32(size));
if (dc->flags_x) {
cris_evaluate_flags(dc);
@@ -2971,6 +2966,7 @@ static void cris_tr_init_disas_context(DisasContextBase
*dcbase, CPUState *cs)
dc->cpu = env_archcpu(env);
dc->ppc = pc_start;
dc->pc = pc_start;
+ dc->mem_index = cpu_mmu_index(env, false);
dc->flags_uptodate = 1;
dc->flags_x = tb_flags & X_FLAG;
dc->cc_x_uptodate = 0;
diff --git a/target/cris/translate_v10.c.inc b/target/cris/translate_v10.c.inc
index 6df599fdce..73fc27c15d 100644
--- a/target/cris/translate_v10.c.inc
+++ b/target/cris/translate_v10.c.inc
@@ -91,8 +91,6 @@ static void gen_store_v10_conditional(DisasContext *dc, TCGv
addr, TCGv val,
static void gen_store_v10(DisasContext *dc, TCGv addr, TCGv val,
unsigned int size)
{
- int mem_index = cpu_mmu_index(&dc->cpu->env, false);
-
/* If we get a fault on a delayslot we must keep the jmp state in
the cpu-state to be able to re-execute the jmp. */
if (dc->delayed_branch == 1) {
@@ -101,11 +99,11 @@ static void gen_store_v10(DisasContext *dc, TCGv addr,
TCGv val,
/* Conditional writes. */
if (dc->flags_x) {
- gen_store_v10_conditional(dc, addr, val, size, mem_index);
+ gen_store_v10_conditional(dc, addr, val, size, dc->mem_index);
return;
}
- tcg_gen_qemu_st_tl(val, addr, mem_index, ctz32(size) | MO_TE);
+ tcg_gen_qemu_st_tl(val, addr, dc->mem_index, ctz32(size) | MO_TE);
}
--
2.34.1
- [PATCH 00/33] hw/core: Introduce CPUClass hook for mmu_index, Richard Henderson, 2024/01/29
- [PATCH 01/33] include/hw/core: Add mmu_index to CPUClass, Richard Henderson, 2024/01/29
- [PATCH 02/33] target/alpha: Split out alpha_env_mmu_index, Richard Henderson, 2024/01/29
- [PATCH 03/33] target/alpha: Populate CPUClass.mmu_index, Richard Henderson, 2024/01/29
- [PATCH 04/33] target/arm: Split out arm_env_mmu_index, Richard Henderson, 2024/01/29
- [PATCH 08/33] target/cris: Populate CPUClass.mmu_index, Richard Henderson, 2024/01/29
- [PATCH 06/33] target/avr: Populate CPUClass.mmu_index, Richard Henderson, 2024/01/29
- [PATCH 07/33] target/cris: Cache mem_index in DisasContext,
Richard Henderson <=
- [PATCH 11/33] target/loongarch: Populate CPUClass.mmu_index, Richard Henderson, 2024/01/29
- [PATCH 09/33] target/hppa: Populate CPUClass.mmu_index, Richard Henderson, 2024/01/29
- [PATCH 12/33] target/loongarch: Rename MMU_IDX_*, Richard Henderson, 2024/01/29
- [PATCH 13/33] target/m68k: Populate CPUClass.mmu_index, Richard Henderson, 2024/01/29
- [PATCH 05/33] target/arm: Populate CPUClass.mmu_index, Richard Henderson, 2024/01/29
- [PATCH 10/33] target/i386: Populate CPUClass.mmu_index, Richard Henderson, 2024/01/29
- [PATCH 16/33] target/mips: Split out mips_env_mmu_index, Richard Henderson, 2024/01/29
- [PATCH 15/33] target/mips: Pass ptw_mmu_idx down from mips_cpu_tlb_fill, Richard Henderson, 2024/01/29
- [PATCH 17/33] target/mips: Populate CPUClass.mmu_index, Richard Henderson, 2024/01/29