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[PULL 09/37] target/arm: Handle PSTATE.ALLINT on taking an exception
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From: |
Peter Maydell |
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Subject: |
[PULL 09/37] target/arm: Handle PSTATE.ALLINT on taking an exception |
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Date: |
Thu, 25 Apr 2024 11:39:30 +0100 |
From: Jinjie Ruan <ruanjinjie@huawei.com>
Set or clear PSTATE.ALLINT on taking an exception to ELx according to the
SCTLR_ELx.SPINTMASK bit.
Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20240407081733.3231820-10-ruanjinjie@huawei.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/helper.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 6b6d8a349a2..5ff9e44649a 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -11733,6 +11733,14 @@ static void arm_cpu_do_interrupt_aarch64(CPUState *cs)
}
}
+ if (cpu_isar_feature(aa64_nmi, cpu)) {
+ if (!(env->cp15.sctlr_el[new_el] & SCTLR_SPINTMASK)) {
+ new_mode |= PSTATE_ALLINT;
+ } else {
+ new_mode &= ~PSTATE_ALLINT;
+ }
+ }
+
pstate_write(env, PSTATE_DAIF | new_mode);
env->aarch64 = true;
aarch64_restore_sp(env, new_el);
--
2.34.1
- [PULL 13/37] hw/intc/arm_gicv3: Add has-nmi property to GICv3 device, (continued)
- [PULL 13/37] hw/intc/arm_gicv3: Add has-nmi property to GICv3 device, Peter Maydell, 2024/04/25
- [PULL 14/37] hw/intc/arm_gicv3_kvm: Not set has-nmi=true for the KVM GICv3, Peter Maydell, 2024/04/25
- [PULL 15/37] hw/intc/arm_gicv3: Add irq non-maskable property, Peter Maydell, 2024/04/25
- [PULL 19/37] hw/intc/arm_gicv3: Handle icv_nmiar1_read() for icc_nmiar1_read(), Peter Maydell, 2024/04/25
- [PULL 21/37] hw/intc/arm_gicv3: Report the NMI interrupt in gicv3_cpuif_update(), Peter Maydell, 2024/04/25
- [PULL 26/37] linux-user/flatload.c: Remove unused bFLT shared-library and ZFLAT code, Peter Maydell, 2024/04/25
- [PULL 29/37] scripts/coccinelle: New script to add ResetType to hold and exit phases, Peter Maydell, 2024/04/25
- [PULL 18/37] hw/intc/arm_gicv3: Add NMI handling CPU interface registers, Peter Maydell, 2024/04/25
- [PULL 33/37] hw/char: Implement STM32L4x5 USART skeleton, Peter Maydell, 2024/04/25
- [PULL 12/37] target/arm: Handle NMI in arm_cpu_do_interrupt_aarch64(), Peter Maydell, 2024/04/25
- [PULL 09/37] target/arm: Handle PSTATE.ALLINT on taking an exception,
Peter Maydell <=
- [PULL 11/37] hw/arm/virt: Wire NMI and VINMI irq lines from GIC to CPU, Peter Maydell, 2024/04/25
- [PULL 16/37] hw/intc/arm_gicv3_redist: Implement GICR_INMIR0, Peter Maydell, 2024/04/25
- [PULL 17/37] hw/intc/arm_gicv3: Implement GICD_INMIR, Peter Maydell, 2024/04/25
- [PULL 20/37] hw/intc/arm_gicv3: Implement NMI interrupt priority, Peter Maydell, 2024/04/25
- [PULL 22/37] hw/intc/arm_gicv3: Report the VINMI interrupt, Peter Maydell, 2024/04/25
- [PULL 23/37] target/arm: Add FEAT_NMI to max, Peter Maydell, 2024/04/25
- [PULL 25/37] hw/dma: avoid apparent overflow in soc_dma_set_request, Peter Maydell, 2024/04/25
- [PULL 24/37] hw/arm/virt: Enable NMI support in the GIC if the CPU has FEAT_NMI, Peter Maydell, 2024/04/25
- [PULL 27/37] hw/misc: Don't special case RESET_TYPE_COLD in npcm7xx_clk, gcr, Peter Maydell, 2024/04/25
- [PULL 28/37] allwinner-i2c, adm1272: Use device_cold_reset() for software-triggered reset, Peter Maydell, 2024/04/25