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[PULL 25/37] hw/dma: avoid apparent overflow in soc_dma_set_request
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From: |
Peter Maydell |
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Subject: |
[PULL 25/37] hw/dma: avoid apparent overflow in soc_dma_set_request |
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Date: |
Thu, 25 Apr 2024 11:39:46 +0100 |
From: Anastasia Belova <abelova@astralinux.ru>
In soc_dma_set_request() we try to set a bit in a uint64_t, but we
do it with "1 << ch->num", which can't set any bits past 31;
any use for a channel number of 32 or more would fail due to
integer overflow.
This doesn't happen in practice for our current use of this code,
because the worst case is when we call soc_dma_init() with an
argument of 32 for the number of channels, and QEMU builds with
-fwrapv so the shift into the sign bit is well-defined. However,
it's obviously not the intended behaviour of the code.
Add casts to force the shift to be done as 64-bit arithmetic,
allowing up to 64 channels.
Found by Linux Verification Center (linuxtesting.org) with SVACE.
Fixes: afbb5194d4 ("Handle on-chip DMA controllers in one place, convert OMAP
DMA to use it.")
Signed-off-by: Anastasia Belova <abelova@astralinux.ru>
Message-id: 20240409115301.21829-1-abelova@astralinux.ru
[PMM: Edit commit message to clarify that this doesn't actually
bite us in our current usage of this code.]
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/dma/soc_dma.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/dma/soc_dma.c b/hw/dma/soc_dma.c
index 3a430057f54..d5c52b804f8 100644
--- a/hw/dma/soc_dma.c
+++ b/hw/dma/soc_dma.c
@@ -209,9 +209,9 @@ void soc_dma_set_request(struct soc_dma_ch_s *ch, int level)
dma->enabled_count += level - ch->enable;
if (level)
- dma->ch_enable_mask |= 1 << ch->num;
+ dma->ch_enable_mask |= (uint64_t)1 << ch->num;
else
- dma->ch_enable_mask &= ~(1 << ch->num);
+ dma->ch_enable_mask &= ~((uint64_t)1 << ch->num);
if (level != ch->enable) {
soc_dma_ch_freq_update(dma);
--
2.34.1
- [PULL 18/37] hw/intc/arm_gicv3: Add NMI handling CPU interface registers, (continued)
- [PULL 18/37] hw/intc/arm_gicv3: Add NMI handling CPU interface registers, Peter Maydell, 2024/04/25
- [PULL 33/37] hw/char: Implement STM32L4x5 USART skeleton, Peter Maydell, 2024/04/25
- [PULL 12/37] target/arm: Handle NMI in arm_cpu_do_interrupt_aarch64(), Peter Maydell, 2024/04/25
- [PULL 09/37] target/arm: Handle PSTATE.ALLINT on taking an exception, Peter Maydell, 2024/04/25
- [PULL 11/37] hw/arm/virt: Wire NMI and VINMI irq lines from GIC to CPU, Peter Maydell, 2024/04/25
- [PULL 16/37] hw/intc/arm_gicv3_redist: Implement GICR_INMIR0, Peter Maydell, 2024/04/25
- [PULL 17/37] hw/intc/arm_gicv3: Implement GICD_INMIR, Peter Maydell, 2024/04/25
- [PULL 20/37] hw/intc/arm_gicv3: Implement NMI interrupt priority, Peter Maydell, 2024/04/25
- [PULL 22/37] hw/intc/arm_gicv3: Report the VINMI interrupt, Peter Maydell, 2024/04/25
- [PULL 23/37] target/arm: Add FEAT_NMI to max, Peter Maydell, 2024/04/25
- [PULL 25/37] hw/dma: avoid apparent overflow in soc_dma_set_request,
Peter Maydell <=
- [PULL 24/37] hw/arm/virt: Enable NMI support in the GIC if the CPU has FEAT_NMI, Peter Maydell, 2024/04/25
- [PULL 27/37] hw/misc: Don't special case RESET_TYPE_COLD in npcm7xx_clk, gcr, Peter Maydell, 2024/04/25
- [PULL 28/37] allwinner-i2c, adm1272: Use device_cold_reset() for software-triggered reset, Peter Maydell, 2024/04/25
- [PULL 32/37] reset: Add RESET_TYPE_SNAPSHOT_LOAD, Peter Maydell, 2024/04/25
- [PULL 34/37] hw/char/stm32l4x5_usart: Enable serial read and write, Peter Maydell, 2024/04/25
- [PULL 35/37] hw/char/stm32l4x5_usart: Add options for serial parameters setting, Peter Maydell, 2024/04/25
- [PULL 31/37] docs/devel/reset: Update to new API for hold and exit phase methods, Peter Maydell, 2024/04/25
- [PULL 36/37] hw/arm: Add the USART to the stm32l4x5 SoC, Peter Maydell, 2024/04/25
- [PULL 30/37] hw, target: Add ResetType argument to hold and exit phase methods, Peter Maydell, 2024/04/25
- [PULL 37/37] tests/qtest: Add tests for the STM32L4x5 USART, Peter Maydell, 2024/04/25