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[PATCH 05/18] bsd-user: Add prototype for RISC-V TLS register setup
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From: |
Ajeet Singh |
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Subject: |
[PATCH 05/18] bsd-user: Add prototype for RISC-V TLS register setup |
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Date: |
Fri, 2 Aug 2024 18:34:10 +1000 |
From: Mark Corbin <mark.corbin@embecsom.com>
Included the prototype for the 'target_cpu_set_tls' function in the
'target_arch.h' header file. This function is responsible for setting
the Thread Local Storage (TLS) register for RISC-V architecture.
Signed-off-by: Mark Corbin <mark.corbin@embecsom.com>
Signed-off-by: Ajeet Singh <itachis@FreeBSD.org>
---
bsd-user/riscv/target_arch.h | 27 +++++++++++++++++++++++++++
1 file changed, 27 insertions(+)
create mode 100644 bsd-user/riscv/target_arch.h
diff --git a/bsd-user/riscv/target_arch.h b/bsd-user/riscv/target_arch.h
new file mode 100644
index 0000000000..26ce07f343
--- /dev/null
+++ b/bsd-user/riscv/target_arch.h
@@ -0,0 +1,27 @@
+/*
+ * RISC-V specific prototypes
+ *
+ * Copyright (c) 2019 Mark Corbin <mark.corbin@embecsom.com>
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef TARGET_ARCH_H
+#define TARGET_ARCH_H
+
+#include "qemu.h"
+
+void target_cpu_set_tls(CPURISCVState *env, target_ulong newtls);
+
+#endif /* TARGET_ARCH_H */
--
2.34.1
- [PATCH 00/18] bsd-user: Comprehensive RISCV support, Ajeet Singh, 2024/08/02
- [PATCH 01/18] bsd-user: Implement RISC-V CPU initialization and main loop, Ajeet Singh, 2024/08/02
- [PATCH 02/18] bsd-user: Add RISC-V CPU execution loop and syscall handling, Ajeet Singh, 2024/08/02
- [PATCH 03/18] bsd-user: Implement RISC-V CPU register cloning and reset functions, Ajeet Singh, 2024/08/02
- [PATCH 04/18] bsd-user: Implement RISC-V TLS register setup, Ajeet Singh, 2024/08/02
- [PATCH 05/18] bsd-user: Add prototype for RISC-V TLS register setup,
Ajeet Singh <=
- [PATCH 06/18] bsd-user: Add RISC-V ELF definitions and hardware capability detection, Ajeet Singh, 2024/08/02
- [PATCH 07/18] bsd-user: Define RISC-V register structures and register copying, Ajeet Singh, 2024/08/02
- [PATCH 08/18] bsd-user: Add RISC-V signal trampoline setup function, Ajeet Singh, 2024/08/02
- [PATCH 09/18] bsd-user: Implement RISC-V sysarch system call emulation, Ajeet Singh, 2024/08/02
- [PATCH 10/18] bsd-user: Add RISC-V thread setup and initialization support, Ajeet Singh, 2024/08/02