Re: [PATCH 01/18] bsd-user: Implement RISC-V CPU initialization and main

qemu-devel

From:	Richard Henderson
Subject:	Re: [PATCH 01/18] bsd-user: Implement RISC-V CPU initialization and main loop
Date:	Fri, 2 Aug 2024 22:41:33 +1000
User-agent:	Mozilla Thunderbird

On 8/2/24 18:34, Ajeet Singh wrote:

+static inline void target_cpu_init(CPURISCVState *env,
+        struct target_pt_regs *regs)
+{
+    int i;
+
+    for (i = 0; i < 32; i++) {


i = 1 as r0 is zero.

Otherwise,
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>


r~

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[PATCH 00/18] bsd-user: Comprehensive RISCV support, Ajeet Singh, 2024/08/02
- [PATCH 01/18] bsd-user: Implement RISC-V CPU initialization and main loop, Ajeet Singh, 2024/08/02
  - Re: [PATCH 01/18] bsd-user: Implement RISC-V CPU initialization and main loop, Richard Henderson <=
- [PATCH 02/18] bsd-user: Add RISC-V CPU execution loop and syscall handling, Ajeet Singh, 2024/08/02
  - Re: [PATCH 02/18] bsd-user: Add RISC-V CPU execution loop and syscall handling, Richard Henderson, 2024/08/02
- [PATCH 03/18] bsd-user: Implement RISC-V CPU register cloning and reset functions, Ajeet Singh, 2024/08/02
  - Re: [PATCH 03/18] bsd-user: Implement RISC-V CPU register cloning and reset functions, Richard Henderson, 2024/08/02
- [PATCH 04/18] bsd-user: Implement RISC-V TLS register setup, Ajeet Singh, 2024/08/02
  - Re: [PATCH 04/18] bsd-user: Implement RISC-V TLS register setup, Richard Henderson, 2024/08/02
- [PATCH 05/18] bsd-user: Add prototype for RISC-V TLS register setup, Ajeet Singh, 2024/08/02
  - Re: [PATCH 05/18] bsd-user: Add prototype for RISC-V TLS register setup, Richard Henderson, 2024/08/02
- [PATCH 06/18] bsd-user: Add RISC-V ELF definitions and hardware capability detection, Ajeet Singh, 2024/08/02
  - Re: [PATCH 06/18] bsd-user: Add RISC-V ELF definitions and hardware capability detection, Richard Henderson, 2024/08/02