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[PATCH v2 02/17] intel_iommu: Make pasid entry type check accurate
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From: |
Zhenzhong Duan |
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Subject: |
[PATCH v2 02/17] intel_iommu: Make pasid entry type check accurate |
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Date: |
Mon, 5 Aug 2024 14:27:12 +0800 |
When guest configures Nested Translation(011b) or First-stage Translation only
(001b), type check passed unaccurately.
Fails the type check in those cases as their simulation isn't supported yet.
Fixes: fb43cf739e1 ("intel_iommu: scalable mode emulation")
Suggested-by: Yi Liu <yi.l.liu@intel.com>
Signed-off-by: Zhenzhong Duan <zhenzhong.duan@intel.com>
Reviewed-by: Clément Mathieu--Drif<clement.mathieu--drif@eviden.com>
---
hw/i386/intel_iommu.c | 12 ++++--------
1 file changed, 4 insertions(+), 8 deletions(-)
diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
index c52912f593..e3465fc27d 100644
--- a/hw/i386/intel_iommu.c
+++ b/hw/i386/intel_iommu.c
@@ -759,20 +759,16 @@ static inline bool vtd_pe_type_check(X86IOMMUState
*x86_iommu,
VTDPASIDEntry *pe)
{
switch (VTD_PE_GET_TYPE(pe)) {
- case VTD_SM_PASID_ENTRY_FLT:
case VTD_SM_PASID_ENTRY_SLT:
- case VTD_SM_PASID_ENTRY_NESTED:
- break;
+ return true;
case VTD_SM_PASID_ENTRY_PT:
- if (!x86_iommu->pt_supported) {
- return false;
- }
- break;
+ return x86_iommu->pt_supported;
+ case VTD_SM_PASID_ENTRY_FLT:
+ case VTD_SM_PASID_ENTRY_NESTED:
default:
/* Unknown type */
return false;
}
- return true;
}
static inline bool vtd_pdire_present(VTDPASIDDirEntry *pdire)
--
2.34.1
- Re: [PATCH v2 01/17] intel_iommu: Use the latest fault reasons defined by spec, (continued)
- [PATCH v2 03/17] intel_iommu: Add a placeholder variable for scalable modern mode, Zhenzhong Duan, 2024/08/05
- Re: [PATCH v2 03/17] intel_iommu: Add a placeholder variable for scalable modern mode, CLEMENT MATHIEU--DRIF, 2024/08/06
- Re: [PATCH v2 03/17] intel_iommu: Add a placeholder variable for scalable modern mode, Duan, Zhenzhong, 2024/08/08
- Re: [PATCH v2 03/17] intel_iommu: Add a placeholder variable for scalable modern mode, CLEMENT MATHIEU--DRIF, 2024/08/08
- RE: [PATCH v2 03/17] intel_iommu: Add a placeholder variable for scalable modern mode, Duan, Zhenzhong, 2024/08/12
- Re: [PATCH v2 03/17] intel_iommu: Add a placeholder variable for scalable modern mode, CLEMENT MATHIEU--DRIF, 2024/08/13
- RE: [PATCH v2 03/17] intel_iommu: Add a placeholder variable for scalable modern mode, Duan, Zhenzhong, 2024/08/13
- Re: [PATCH v2 03/17] intel_iommu: Add a placeholder variable for scalable modern mode, CLEMENT MATHIEU--DRIF, 2024/08/13
[PATCH v2 02/17] intel_iommu: Make pasid entry type check accurate,
Zhenzhong Duan <=
[PATCH v2 04/17] intel_iommu: Flush stage-2 cache in PASID-selective PASID-based iotlb invalidation, Zhenzhong Duan, 2024/08/05
- Re: [PATCH v2 04/17] intel_iommu: Flush stage-2 cache in PASID-selective PASID-based iotlb invalidation, CLEMENT MATHIEU--DRIF, 2024/08/06
- Re: [PATCH v2 04/17] intel_iommu: Flush stage-2 cache in PASID-selective PASID-based iotlb invalidation, Duan, Zhenzhong, 2024/08/08
- Re: [PATCH v2 04/17] intel_iommu: Flush stage-2 cache in PASID-selective PASID-based iotlb invalidation, CLEMENT MATHIEU--DRIF, 2024/08/08
- RE: [PATCH v2 04/17] intel_iommu: Flush stage-2 cache in PASID-selective PASID-based iotlb invalidation, Duan, Zhenzhong, 2024/08/12
- Re: [PATCH v2 04/17] intel_iommu: Flush stage-2 cache in PASID-selective PASID-based iotlb invalidation, CLEMENT MATHIEU--DRIF, 2024/08/13
- Re: [PATCH v2 04/17] intel_iommu: Flush stage-2 cache in PASID-selective PASID-based iotlb invalidation, CLEMENT MATHIEU--DRIF, 2024/08/13
Re: [PATCH v2 04/17] intel_iommu: Flush stage-2 cache in PASID-selective PASID-based iotlb invalidation, Yi Liu, 2024/08/14