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[PATCH v3 20/20] linux-user: Add RISC-V zicfilp support in VDSO
From: |
Deepak Gupta |
Subject: |
[PATCH v3 20/20] linux-user: Add RISC-V zicfilp support in VDSO |
Date: |
Tue, 6 Aug 2024 17:06:51 -0700 |
Add zicfilp support in VDSO. VDSO functions need lpad instruction
so that userspace could call this function when landing pad extension is
enabled. This solution only works when toolchain always use landing pad
label 1.
Otherwise, If extension is not enabled, lpad instructions will be lui
instructions with rd=x0 (which is nop). Prebuilt VDSO is still
compatible with RISC-V core w/o zicfilp extension.
Signed-off-by: Jim Shu <jim.shu@sifive.com>
Signed-off-by: Deepak Gupta <debug@rivosinc.com>
---
linux-user/riscv/vdso-64.so | Bin 3944 -> 4128 bytes
linux-user/riscv/vdso.S | 50 ++++++++++++++++++++++++++++++++++++
2 files changed, 50 insertions(+)
diff --git a/linux-user/riscv/vdso-64.so b/linux-user/riscv/vdso-64.so
index
ae49f5b043b5941b9d304a056c2b50c185f413b0..cd7f2fa7bdb811af6be2dcc3fb9601b66e3d1c81
100755
GIT binary patch
delta 1345
zcmah}O=uHA6rRa8*`3W#v-vSWgUvy(QL#}%mV&j76iPuQBHAj2(ng|zmM)E!P>`g>
ziy+eQP!K%yD2kv2Jb7q5_;(V#<f8T>2zrPIp$E0T*_|nLFFu%g^L_K)%k2BfxBcts
zwSKzU%uIMvDl|QN=xp<WSxBkG7O6?t!5&mSxH{CqZapIS5in@ND0&^M9SwtYn2kCl
z8HHvbTIYee+1S|&oZsNl6@EhD=NK-I`TfVcovANRA6MVpdHd;BIWn<tz;C}Zg!f#o
zJIeOs$1M@)*Wc|0j<Y-<ig*^WdPuKL`0SmKqyiq##X<Z^OE9+jz3uoXh2tNAc{aFo
z1twr<QCRm}!4()%@Eu+GDUKoG>4}g4*$}@d(n<~qepB*LP!3)Siz)<!cU)L~kXC{}
zEqLOxKPmXG%f8cUD^<!G_?jY`yo4d|;kbMX*GF*m<L!yoO|MGplL+N?0uP|A=~d*e
zHVAQWSlx}&F5K8<AH_U!-zdg#{GVyuzc7Q_Vx?MIB6I?e-o>SSu5ui{`}Ri4l{qVG
z<))V_rE;ZO#UoHP&Zd{==Wom%v$EK`eUMXAv;*hV1Wm$<8dtCYs1tO{Mm~~-=ZGxa
z<BEpgVQ6uMk)*A4Qbe7gH5*}xprDP>jpj-e9%`|fX?zbQKeuJaBedlj?wn7H+zXnl
z+6N3On@wEY6ZY=Tcmf7X)L-B&?+<q+-wWQ|H=hOXuJ8}RyE}+CAdkP(XK2SI=J0*Q
z-CCqns+~DMS-yO9fgGs8S6}+Sm1w<YuP7ab3>M^(KWxa1Nj(DZ`~!MYOa>phK%U8T
zbfFM1nH*fK8zMQjS!g4|p|!;V8Z`BtS@y!IU|yFKn)JeIFwbQ2i_i|5tR_lP0~#_7
pnM$drU_4|p`G+?Pw?igvKsz+7r*-ESGZggRJRA2r@IJ6$-#>;G!0Z43
delta 1236
zcmZux&1(};5TBP#+z*pYV+<*_)IAj1YN_?B+bY<^rnX2aRgfZHEGbA2QZyn~#MXa6
z69zo>Q1McbLL?%ocu2)V4jv*F!CQ|xnnMLet@AeXqAU))otfYJy|4M$HK*Q{?-jj;
zzFD!24I_@VKv0a~RwP*{I_d3w;EB@E*7O6Uf;7sa>HGB{<AWFz$(R#rvRWEP#3-gj
z=kh_C&}d9dUxAJB?DWLN7i-UF5AA;Y{Ap&b@ba}>XUh-Cou=~6m1b2gB-#DFx9A!2
zLL__`q}b;tKwVy%#A+&d0)Qt2<9$E(n(OP#|HVGj;Vb(!Jnn^O9`m|=HV73ypSJ_~
z<O2|fJRcb5i6e}!D;#fWJy$=lXD}<ltX0Kge2VdkkAIHwS3Z8Z)X;Lmd_cFEA<8=5
z3>{6VtH|v2)99wz{?bNB7jqeM)ifG;D@Xo~6$*{frvJ5_f9#bOCr+W3+&Ha4qi9He
z`aFGZFXXa!K@5`_!U4;{c`Jrnfi7ItJ4G3v>4^@ll@B7dM5F9h@S~p4LQq9vBn42^
z6PgYw(n%q6kkCx1d)fjA=g8j=lUShHyjQ?)jZ>c0vk;|y1vK_lb*f|98Q<a9Dg1<I
z(5|Y4cw(IS{)}HEJVyHiUb5rMGWY&0-6zKXYT_~D{_L$X?yrs_<E<JZU&?zLa(}9t
z4i8YNglu-<^o7ju<$*=$zE^r^y%V@%J9s_Z7E|F+dJrFlk6Efc>H&Nc9x~NiEBHO^
znyS~TI1+KqRtw@1d8*G+xEXP+8h24Gh(97jmTIbc5YN~{ri!eCOSWrHa-1h|({^L3
qZ<NlUh`Ofw^Ne9S>WX$;ijJCP(|ap?q2JVD+=;fE1#ar668QsJ{<Wt7
diff --git a/linux-user/riscv/vdso.S b/linux-user/riscv/vdso.S
index c37275233a..d0817c58ce 100644
--- a/linux-user/riscv/vdso.S
+++ b/linux-user/riscv/vdso.S
@@ -14,6 +14,52 @@
#endif
#include "vdso-asmoffset.h"
+/* GNU_PROPERTY_RISCV64_* macros from elf.h for use in asm code. */
+#define FEATURE_1_AND 0xc0000000
+
+#define GNU_PROPERTY(type, value) \
+ .section .note.gnu.property, "a"; \
+ .p2align 3; \
+ .word 4; \
+ .word 16; \
+ .word 5; \
+ .asciz "GNU"; \
+ .word type; \
+ .word 4; \
+ .word value; \
+ .word 0; \
+ .text
+
+/* Add GNU property note with the supported features to all asm code
+ where sysdep.h is included. */
+#undef __VALUE_FOR_FEATURE_1_AND
+#if defined (__riscv_zicfilp) || defined (__riscv_zicfiss)
+# if defined (__riscv_zicfilp)
+# if defined (__riscv_zicfiss)
+# define __VALUE_FOR_FEATURE_1_AND 0x3
+# else
+# define __VALUE_FOR_FEATURE_1_AND 0x1
+# endif
+# else
+# if defined (__riscv_zicfiss)
+# define __VALUE_FOR_FEATURE_1_AND 0x2
+# else
+# error "What?"
+# endif
+# endif
+#endif
+
+#if defined (__VALUE_FOR_FEATURE_1_AND)
+GNU_PROPERTY (FEATURE_1_AND, __VALUE_FOR_FEATURE_1_AND)
+#endif
+#undef __VALUE_FOR_FEATURE_1_AND
+
+#ifdef __riscv_zicfilp
+# define LPAD lpad 1
+#else
+# define LPAD
+#endif
+
.text
.macro endf name
@@ -29,6 +75,7 @@
.macro vdso_syscall name, nr
\name:
+ LPAD
raw_syscall \nr
ret
endf \name
@@ -36,6 +83,7 @@ endf \name
__vdso_gettimeofday:
.cfi_startproc
+ LPAD
#ifdef __NR_gettimeofday
raw_syscall __NR_gettimeofday
ret
@@ -86,6 +134,7 @@ vdso_syscall __vdso_getcpu, __NR_getcpu
__vdso_flush_icache:
/* qemu does not need to flush the icache */
+ LPAD
li a0, 0
ret
endf __vdso_flush_icache
@@ -181,6 +230,7 @@ endf __vdso_flush_icache
nop
__vdso_rt_sigreturn:
+ LPAD
raw_syscall __NR_rt_sigreturn
endf __vdso_rt_sigreturn
--
2.44.0
- Re: [PATCH v3 12/20] target/riscv: implement zicfiss instructions, (continued)
- [PATCH v3 17/20] disas/riscv: enable disassembly for compressed sspush/sspopchk, Deepak Gupta, 2024/08/06
- [PATCH v3 09/20] target/riscv: Add zicfiss extension, Deepak Gupta, 2024/08/06
- [PATCH v3 11/20] target/riscv: tb flag for shadow stack instructions, Deepak Gupta, 2024/08/06
- [PATCH v3 13/20] target/riscv: compressed encodings for sspush and sspopchk, Deepak Gupta, 2024/08/06
- [PATCH v3 19/20] linux-user: permit RISC-V CFI dynamic entry in VDSO, Deepak Gupta, 2024/08/06
- [PATCH v3 20/20] linux-user: Add RISC-V zicfilp support in VDSO,
Deepak Gupta <=
- [PATCH v3 03/20] target/riscv: Introduce elp state and enabling controls for zicfilp, Deepak Gupta, 2024/08/06
- [PATCH v3 06/20] target/riscv: tracking indirect branches (fcfi) for zicfilp, Deepak Gupta, 2024/08/06
- [PATCH v3 08/20] disas/riscv: enabled `lpad` disassembly, Deepak Gupta, 2024/08/06