Re: [PATCH v3 10/20] target/riscv: introduce ssp and enabling controls for zicfiss

[Richard Henderson]

On 8/7/24 12:11, Richard Henderson wrote:
> On 8/7/24 10:06, Deepak Gupta wrote:
> > diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> > index a5a969a377..d72d6289fb 100644
> > --- a/target/riscv/csr.c
> > +++ b/target/riscv/csr.c
> > @@ -185,6 +185,47 @@ static RISCVException zcmt(CPURISCVState *env, int csrno)
> >       return RISCV_EXCP_NONE;
> >   }
> > +static RISCVException cfi_ss(CPURISCVState *env, int csrno)
> > +{
> > +    /* no cfi extension, access to csr is illegal */
> > +    if (!env_archcpu(env)->cfg.ext_zicfiss) {
> > +        return RISCV_EXCP_ILLEGAL_INST;
> > +    }
> > +    /*
> > +     * CONFIG_USER_MODE always allow access for now. Better for user mode only
> > +     * functionality
> > +     */
>
> In the next patch you add ubcfien, which would apply here.

... anyway, surely cpu_get_bcfien() is the right check anyway?


r~