Re: [PATCH v3 12/20] target/riscv: implement zicfiss instructions

[Deepak Gupta]

On Wed, Aug 07, 2024 at 12:56:46PM +1000, Richard Henderson wrote:
> On 8/7/24 12:39, Richard Henderson wrote:
> > > +static bool trans_sspopchk(DisasContext *ctx, arg_sspopchk *a)
> > > +{
> > > +    /* default for qemu-user, use regular RW memory and thus mmu_idx=0 */
> > > +    int ss_mmu_idx = 0;
> >
> > This can't be right, since 0 is M_MODE.
>
> I'm wrong about m-mode here, but "0" is certainly not right.

I followed `riscv_env_mmu_index` here. If CONFIG_USER_ONLY, it returns 0.
For qemu-user, I didn't bother to protect shadow stack from normal stores.
And simply used index 0.

> I strongly suspect you want "ctx->mem_idx | MMU_IDX_SS_ACCESS",
> once you add that bit in a few patches.
>
>
> r~