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[PULL 09/11] target/arm: add support for PMUv3 64-bit PMCCNTR in AArch32
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From: |
Peter Maydell |
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Subject: |
[PULL 09/11] target/arm: add support for PMUv3 64-bit PMCCNTR in AArch32 mode |
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Date: |
Fri, 9 Aug 2024 19:08:33 +0100 |
From: Alex Richardson <alexrichardson@google.com>
In the PMUv3, a new AArch32 64-bit (MCRR/MRRC) accessor for the
PMCCNTR was added. In QEMU we forgot to implement this, so only
provide the 32-bit accessor. Since we have a 64-bit PMCCNTR
sysreg for AArch64, adding the 64-bit AArch32 version is easy.
We add the PMCCNTR to the v8_cp_reginfo because PMUv3 was added
in the ARMv8 architecture. This is consistent with how we
handle the existing PMCCNTR support, where we always implement
it for all v7 CPUs. This is arguably something we should
clean up so it is gated on ARM_FEATURE_PMU and/or an ID
register check for the relevant PMU version, but we should
do that as its own tidyup rather than being inconsistent between
this PMCCNTR accessor and the others.
See
https://developer.arm.com/documentation/ddi0601/2024-06/AArch32-Registers/PMCCNTR--Performance-Monitors-Cycle-Count-Register?lang=en
Signed-off-by: Alex Richardson <alexrichardson@google.com>
Message-id: 20240801220328.941866-1-alexrichardson@google.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/helper.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 8fb4b474e83..94900667c33 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -5952,6 +5952,12 @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
.access = PL1_RW, .accessfn = access_trap_aa32s_el1,
.writefn = sdcr_write,
.fieldoffset = offsetoflow32(CPUARMState, cp15.mdcr_el3) },
+ { .name = "PMCCNTR", .state = ARM_CP_STATE_AA32,
+ .type = ARM_CP_ALIAS | ARM_CP_IO | ARM_CP_64BIT,
+ .cp = 15, .crm = 9, .opc1 = 0,
+ .access = PL0_RW, .resetvalue = 0, .fgt = FGT_PMCCNTR_EL0,
+ .readfn = pmccntr_read, .writefn = pmccntr_write,
+ .accessfn = pmreg_access_ccntr },
};
/* These are present only when EL1 supports AArch32 */
--
2.34.1
- [PULL 00/11] target-arm queue, Peter Maydell, 2024/08/09
- [PULL 01/11] target/arm: Fix BTI versus CF_PCREL, Peter Maydell, 2024/08/09
- [PULL 02/11] include: Fix typo in name of MAKE_IDENTFIER macro, Peter Maydell, 2024/08/09
- [PULL 03/11] docs/specs/rocker.txt: Convert to rST, Peter Maydell, 2024/08/09
- [PULL 04/11] docs/interop/nbd.txt: Convert to rST, Peter Maydell, 2024/08/09
- [PULL 05/11] docs/interop/parallels.txt: Convert to rST, Peter Maydell, 2024/08/09
- [PULL 06/11] docs/interop/prl-xml.txt: Convert to rST, Peter Maydell, 2024/08/09
- [PULL 07/11] docs/interop/prl-xml.rst: Fix minor grammar nits, Peter Maydell, 2024/08/09
- [PULL 08/11] docs: Typo fix in live disk backup, Peter Maydell, 2024/08/09
- [PULL 09/11] target/arm: add support for PMUv3 64-bit PMCCNTR in AArch32 mode,
Peter Maydell <=
- Re: [PULL 09/11] target/arm: add support for PMUv3 64-bit PMCCNTR in AArch32 mode, Richard Henderson, 2024/08/11
- Re: [PULL 09/11] target/arm: add support for PMUv3 64-bit PMCCNTR in AArch32 mode, Peter Maydell, 2024/08/12
- Re: [PULL 09/11] target/arm: add support for PMUv3 64-bit PMCCNTR in AArch32 mode, Peter Maydell, 2024/08/12
- Re: [PULL 09/11] target/arm: add support for PMUv3 64-bit PMCCNTR in AArch32 mode, Alex Bennée, 2024/08/12
- Re: [PULL 09/11] target/arm: add support for PMUv3 64-bit PMCCNTR in AArch32 mode, Peter Maydell, 2024/08/12
- Re: [PULL 09/11] target/arm: add support for PMUv3 64-bit PMCCNTR in AArch32 mode, Alex Bennée, 2024/08/13
[PULL 10/11] hw/core/ptimer: fix timer zero period condition for freq > 1GHz, Peter Maydell, 2024/08/09
[PULL 11/11] arm/virt: place power button pin number on a define, Peter Maydell, 2024/08/09