Re: [PATCH 00/17] target/arm: AdvSIMD decodetree conversion, part 4

[Peter Maydell]

On Wed, 17 Jul 2024 at 07:09, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> Flush before the queue gets too big.
> Also, there's a bug fix in patch 14.
>
> r~
>
> Richard Henderson (17):
>   target/arm: Use tcg_gen_extract2_i64 for EXT
>   target/arm: Convert EXT to decodetree
>   target/arm: Convert TBL, TBX to decodetree
>   target/arm: Convert UZP, TRN, ZIP to decodetree
>   target/arm: Simplify do_reduction_op
>   target/arm: Convert ADDV, *ADDLV, *MAXV, *MINV to decodetree
>   target/arm: Convert FMAXNMV, FMINNMV, FMAXV, FMINV to decodetree
>   target/arm: Convert FMOVI (scalar, immediate) to decodetree
>   target/arm: Convert MOVI, FMOV, ORR, BIC (vector immediate) to
>     decodetree
>   target/arm: Introduce gen_gvec_sshr, gen_gvec_ushr
>   target/arm: Fix whitespace near gen_srshr64_i64
>   target/arm: Convert handle_vec_simd_shri to decodetree
>   target/arm: Convet handle_vec_simd_shli to decodetree
>   target/arm: Clear high SVE elements in handle_vec_simd_wshli
>   target/arm: Use {,s}extract in handle_vec_simd_wshli
>   target/arm: Convert SSHLL, USHLL to decodetree
>   target/arm: Push tcg_rnd into handle_shri_with_rndacc

Other than the need-to-avoid-shift-by-negative nits in
patches 12 and 13, whole series

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>

thanks
-- PMM