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[PATCH v1 15/15] tcg/riscv: Enable vector TCG host-native
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From: |
LIU Zhiwei |
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Subject: |
[PATCH v1 15/15] tcg/riscv: Enable vector TCG host-native |
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Date: |
Tue, 13 Aug 2024 19:34:36 +0800 |
From: TANG Tiancheng <tangtiancheng.ttc@alibaba-inc.com>
Signed-off-by: TANG Tiancheng <tangtiancheng.ttc@alibaba-inc.com>
Reviewed-by: Liu Zhiwei <zhiwei_liu@linux.alibaba.com>
---
tcg/riscv/tcg-target.h | 10 +++++++---
1 file changed, 7 insertions(+), 3 deletions(-)
diff --git a/tcg/riscv/tcg-target.h b/tcg/riscv/tcg-target.h
index eb5129a976..fe6c50e49e 100644
--- a/tcg/riscv/tcg-target.h
+++ b/tcg/riscv/tcg-target.h
@@ -143,9 +143,13 @@ typedef enum {
#define TCG_TARGET_HAS_tst 0
/* vector instructions */
-#define TCG_TARGET_HAS_v64 0
-#define TCG_TARGET_HAS_v128 0
-#define TCG_TARGET_HAS_v256 0
+extern int riscv_vlen;
+#define have_rvv ((cpuinfo & CPUINFO_ZVE64X) && \
+ (riscv_vlen >= 64))
+
+#define TCG_TARGET_HAS_v64 have_rvv
+#define TCG_TARGET_HAS_v128 have_rvv
+#define TCG_TARGET_HAS_v256 have_rvv
#define TCG_TARGET_HAS_andc_vec 0
#define TCG_TARGET_HAS_orc_vec 0
#define TCG_TARGET_HAS_nand_vec 0
--
2.43.0
- Re: [PATCH v1 09/15] tcg/riscv: Implement vector cmp ops, (continued)
- [PATCH v1 10/15] tcg/riscv: Implement vector not/neg ops, LIU Zhiwei, 2024/08/13
- [PATCH v1 11/15] tcg/riscv: Implement vector sat/mul ops, LIU Zhiwei, 2024/08/13
- [PATCH v1 12/15] tcg/riscv: Implement vector min/max ops, LIU Zhiwei, 2024/08/13
- [PATCH v1 13/15] tcg/riscv: Implement vector shs/v ops, LIU Zhiwei, 2024/08/13
- [PATCH v1 14/15] tcg/riscv: Implement vector roti/v/x shi ops, LIU Zhiwei, 2024/08/13
- [PATCH v1 15/15] tcg/riscv: Enable vector TCG host-native,
LIU Zhiwei <=