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Re: [PATCH v1 03/15] tcg: Fix register allocation constraints
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From: |
Richard Henderson |
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Subject: |
Re: [PATCH v1 03/15] tcg: Fix register allocation constraints |
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Date: |
Wed, 14 Aug 2024 12:04:13 +1000 |
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User-agent: |
Mozilla Thunderbird |
On 8/14/24 10:58, LIU Zhiwei wrote:
Thus if we want to use all registers of vectors, we have to add a dynamic constraint on
register allocation based on IR types.
My comment vs patch 4 is that you can't do that, at least not without large
changes to TCG.
In addition, I said that the register pressure on vector regs is not high enough to
justify such changes. There is, so far, little benefit in having more than 4 or 5 vector
registers, much less 32. Thus 7 (lmul 4, omitting v0) is sufficient.
r~
- [PATCH v1 00/15] tcg/riscv: Add support for vector, LIU Zhiwei, 2024/08/13
- [PATCH v1 01/15] util: Add RISC-V vector extension probe in cpuinfo, LIU Zhiwei, 2024/08/13
- [PATCH v1 02/15] tcg/op-gvec: Fix iteration step in 32-bit operation, LIU Zhiwei, 2024/08/13
- [PATCH v1 03/15] tcg: Fix register allocation constraints, LIU Zhiwei, 2024/08/13
- Re: [PATCH v1 03/15] tcg: Fix register allocation constraints, Richard Henderson, 2024/08/13
- Re: [PATCH v1 03/15] tcg: Fix register allocation constraints, LIU Zhiwei, 2024/08/13
- Re: [PATCH v1 03/15] tcg: Fix register allocation constraints,
Richard Henderson <=
- Re: [PATCH v1 03/15] tcg: Fix register allocation constraints, LIU Zhiwei, 2024/08/13
- Re: [PATCH v1 03/15] tcg: Fix register allocation constraints, Richard Henderson, 2024/08/13
- Re: [PATCH v1 03/15] tcg: Fix register allocation constraints, LIU Zhiwei, 2024/08/13
- Re: [PATCH v1 03/15] tcg: Fix register allocation constraints, Richard Henderson, 2024/08/14
- Re: [PATCH v1 03/15] tcg: Fix register allocation constraints, LIU Zhiwei, 2024/08/14
[PATCH v1 04/15] tcg/riscv: Add basic support for vector, LIU Zhiwei, 2024/08/13
[PATCH v1 05/15] tcg/riscv: Add riscv vset{i}vli support, LIU Zhiwei, 2024/08/13