[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PATCH v2 12/17] bsd-user: Add generic RISC-V64 target definitions
|
From: |
Ajeet Singh |
|
Subject: |
[PATCH v2 12/17] bsd-user: Add generic RISC-V64 target definitions |
|
Date: |
Sat, 17 Aug 2024 03:09:44 +1000 |
From: Warner Losh <imp@bsdimp.com>
Added a generic definition for RISC-V64 target-specific details.
Implemented the 'regpairs_aligned' function,which returns 'false'
to indicate that register pairs are not aligned in the RISC-V64 ABI.
Signed-off-by: Warner Losh <imp@bsdimp.com>
Signed-off-by: Ajeet Singh <itachis@FreeBSD.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
bsd-user/riscv/target.h | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
create mode 100644 bsd-user/riscv/target.h
diff --git a/bsd-user/riscv/target.h b/bsd-user/riscv/target.h
new file mode 100644
index 0000000000..036ddd185e
--- /dev/null
+++ b/bsd-user/riscv/target.h
@@ -0,0 +1,20 @@
+/*
+ * Riscv64 general target stuff that's common to all aarch details
+ *
+ * Copyright (c) 2022 M. Warner Losh <imp@bsdimp.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#ifndef TARGET_H
+#define TARGET_H
+
+/*
+ * riscv64 ABI does not 'lump' the registers for 64-bit args.
+ */
+static inline bool regpairs_aligned(void *cpu_env)
+{
+ return false;
+}
+
+#endif /* TARGET_H */
--
2.34.1
- [PATCH v2 00/17] bsd-user: Comprehensive RISCV Support, Ajeet Singh, 2024/08/16
- [PATCH v2 01/17] bsd-user: Implement RISC-V CPU initialization and main loop, Ajeet Singh, 2024/08/16
- [PATCH v2 02/17] bsd-user: Add RISC-V CPU execution loop and syscall handling, Ajeet Singh, 2024/08/16
- [PATCH v2 03/17] bsd-user: Implement RISC-V CPU register cloning and reset functions, Ajeet Singh, 2024/08/16
- [PATCH v2 07/17] bsd-user: Add RISC-V signal trampoline setup function, Ajeet Singh, 2024/08/16
- [PATCH v2 11/17] bsd-user: Define RISC-V system call structures and constants, Ajeet Singh, 2024/08/16
- [PATCH v2 04/17] bsd-user: Implement RISC-V TLS register setup, Ajeet Singh, 2024/08/16
- [PATCH v2 12/17] bsd-user: Add generic RISC-V64 target definitions,
Ajeet Singh <=
- [PATCH v2 05/17] bsd-user: Add RISC-V ELF definitions and hardware capability detection, Ajeet Singh, 2024/08/16
- [PATCH v2 09/17] bsd-user: Add RISC-V thread setup and initialization support, Ajeet Singh, 2024/08/16
- [PATCH v2 06/17] bsd-user: Define RISC-V register structures and register copying, Ajeet Singh, 2024/08/16
- [PATCH v2 08/17] bsd-user: Implement RISC-V sysarch system call emulation, Ajeet Singh, 2024/08/16
- [PATCH v2 10/17] bsd-user: Define RISC-V VM parameters and helper functions, Ajeet Singh, 2024/08/16
- [PATCH v2 13/17] bsd-user: Define RISC-V signal handling structures and constants, Ajeet Singh, 2024/08/16
- [PATCH v2 14/17] bsd-user: Implement RISC-V signal trampoline setup functions, Ajeet Singh, 2024/08/16
- [PATCH v2 16/17] bsd-user: Implement set_mcontext and get_ucontext_sigreturn for RISCV, Ajeet Singh, 2024/08/16
- [PATCH v2 15/17] bsd-user: Implement 'get_mcontext' for RISC-V, Ajeet Singh, 2024/08/16