Re: [PATCH 2/2] hw/char: sifive_uart: Print uart charecters async

[Alistair Francis]

On Thu, Aug 15, 2024 at 6:27 PM Mark Cave-Ayland
<mark.cave-ayland@ilande.co.uk> wrote:
>
> On 15/08/2024 02:54, Alistair Francis wrote:
>
> > The current approach of using qemu_chr_fe_write() and ignoring the
> > return values results in dropped charecters [1].
> >
> > Let's update the SiFive UART to use a async sifive_uart_xmit() function
> > to transmit the charecters and apply back preassure to the guest with
> > the SIFIVE_UART_TXFIFO_FULL status.
> >
> > This should avoid dropped charecters and more realisiticly model the
> > hardware.
> >
> > 1: https://gitlab.com/qemu-project/qemu/-/issues/2114
> >
> > Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> > ---
> >   include/hw/char/sifive_uart.h | 17 +++++++-
> >   hw/char/sifive_uart.c         | 81 +++++++++++++++++++++++++++++++++--
> >   2 files changed, 92 insertions(+), 6 deletions(-)
> >
> > diff --git a/include/hw/char/sifive_uart.h b/include/hw/char/sifive_uart.h
> > index 7f6c79f8bd..73379457a0 100644
> > --- a/include/hw/char/sifive_uart.h
> > +++ b/include/hw/char/sifive_uart.h
> > @@ -48,9 +48,13 @@ enum {
> >       SIFIVE_UART_IP_RXWM       = 2  /* Receive watermark interrupt pending 
> > */
> >   };
> >
> > +#define SIFIVE_UART_TXFIFO_FULL    0x80000000
> > +
> >   #define SIFIVE_UART_GET_TXCNT(txctrl)   ((txctrl >> 16) & 0x7)
> >   #define SIFIVE_UART_GET_RXCNT(rxctrl)   ((rxctrl >> 16) & 0x7)
> > +
> >   #define SIFIVE_UART_RX_FIFO_SIZE 8
> > +#define SIFIVE_UART_TX_FIFO_SIZE 8
> >
> >   #define TYPE_SIFIVE_UART "riscv.sifive.uart"
> >   OBJECT_DECLARE_SIMPLE_TYPE(SiFiveUARTState, SIFIVE_UART)
> > @@ -63,13 +67,22 @@ struct SiFiveUARTState {
> >       qemu_irq irq;
> >       MemoryRegion mmio;
> >       CharBackend chr;
> > -    uint8_t rx_fifo[SIFIVE_UART_RX_FIFO_SIZE];
> > -    uint8_t rx_fifo_len;
> > +
> > +    uint32_t txfifo;
> >       uint32_t ie;
> >       uint32_t ip;
> >       uint32_t txctrl;
> >       uint32_t rxctrl;
> >       uint32_t div;
> > +
> > +    uint8_t rx_fifo[SIFIVE_UART_RX_FIFO_SIZE];
> > +    uint8_t rx_fifo_len;
> > +
> > +    uint8_t tx_fifo[SIFIVE_UART_TX_FIFO_SIZE];
> > +    uint32_t tx_level;
> > +
> > +    QEMUTimer *fifo_trigger_handle;
> > +    uint64_t char_tx_time;
> >   };
> >
> >   SiFiveUARTState *sifive_uart_create(MemoryRegion *address_space, hwaddr 
> > base,
> > diff --git a/hw/char/sifive_uart.c b/hw/char/sifive_uart.c
> > index 7fc6787f69..f517500df4 100644
> > --- a/hw/char/sifive_uart.c
> > +++ b/hw/char/sifive_uart.c
> > @@ -64,6 +64,64 @@ static void sifive_uart_update_irq(SiFiveUARTState *s)
> >       }
> >   }
> >
> > +static gboolean sifive_uart_xmit(void *do_not_use, GIOCondition cond,
> > +                                 void *opaque)
> > +{
> > +    SiFiveUARTState *s = opaque;
> > +    int ret;
> > +
> > +    /* instant drain the fifo when there's no back-end */
> > +    if (!qemu_chr_fe_backend_connected(&s->chr)) {
> > +        s->tx_level = 0;
> > +        return G_SOURCE_REMOVE;
> > +    }
> > +
> > +    ret = qemu_chr_fe_write(&s->chr, s->tx_fifo, s->tx_level);
> > +
> > +    if (ret >= 0) {
> > +        s->tx_level -= ret;
> > +        memmove(s->tx_fifo, s->tx_fifo + ret, s->tx_level);
> > +    }
> > +
> > +    if (s->tx_level) {
> > +        guint r = qemu_chr_fe_add_watch(&s->chr, G_IO_OUT | G_IO_HUP,
> > +                                        sifive_uart_xmit, s);
> > +        if (!r) {
> > +            s->tx_level = 0;
> > +            return G_SOURCE_REMOVE;
> > +        }
> > +    }
> > +
> > +    /* Clear the TX Full bit */
> > +    if (s->tx_level != SIFIVE_UART_TX_FIFO_SIZE) {
> > +        s->txfifo &= ~SIFIVE_UART_TXFIFO_FULL;
> > +    }
> > +
> > +    sifive_uart_update_irq(s);
> > +    return G_SOURCE_REMOVE;
> > +}
> > +
> > +static void sifive_uart_write_tx_fifo(SiFiveUARTState *s, const uint8_t 
> > *buf,
> > +                                      int size)
> > +{
> > +    uint64_t current_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
> > +
> > +    if (size > SIFIVE_UART_TX_FIFO_SIZE - s->tx_level) {
> > +        size = SIFIVE_UART_TX_FIFO_SIZE - s->tx_level;
> > +        qemu_log_mask(LOG_GUEST_ERROR, "sifive_uart: TX FIFO overflow");
> > +    }
> > +
> > +    memcpy(s->tx_fifo + s->tx_level, buf, 1);
> > +    s->tx_level += 1;
> > +
> > +    if (s->tx_level == SIFIVE_UART_TX_FIFO_SIZE) {
> > +        s->txfifo |= SIFIVE_UART_TXFIFO_FULL;
> > +    }
> > +
> > +    timer_mod(s->fifo_trigger_handle, current_time +
> > +              (s->char_tx_time * 4));
> > +}
> > +
> >   static uint64_t
> >   sifive_uart_read(void *opaque, hwaddr addr, unsigned int size)
> >   {
> > @@ -82,7 +140,7 @@ sifive_uart_read(void *opaque, hwaddr addr, unsigned int 
> > size)
> >           return 0x80000000;
> >
> >       case SIFIVE_UART_TXFIFO:
> > -        return 0; /* Should check tx fifo */
> > +        return s->txfifo;
> >       case SIFIVE_UART_IE:
> >           return s->ie;
> >       case SIFIVE_UART_IP:
> > @@ -106,12 +164,10 @@ sifive_uart_write(void *opaque, hwaddr addr,
> >   {
> >       SiFiveUARTState *s = opaque;
> >       uint32_t value = val64;
> > -    unsigned char ch = value;
> >
> >       switch (addr) {
> >       case SIFIVE_UART_TXFIFO:
> > -        qemu_chr_fe_write(&s->chr, &ch, 1);
> > -        sifive_uart_update_irq(s);
> > +        sifive_uart_write_tx_fifo(s, (uint8_t *) &value, 1);
> >           return;
> >       case SIFIVE_UART_IE:
> >           s->ie = val64;
> > @@ -131,6 +187,13 @@ sifive_uart_write(void *opaque, hwaddr addr,
> >                     __func__, (int)addr, (int)value);
> >   }
> >
> > +static void fifo_trigger_update(void *opaque)
> > +{
> > +    SiFiveUARTState *s = opaque;
> > +
> > +    sifive_uart_xmit(NULL, G_IO_OUT, s);
> > +}
> > +
> >   static const MemoryRegionOps sifive_uart_ops = {
> >       .read = sifive_uart_read,
> >       .write = sifive_uart_write,
> > @@ -197,6 +260,9 @@ static void sifive_uart_realize(DeviceState *dev, Error 
> > **errp)
> >   {
> >       SiFiveUARTState *s = SIFIVE_UART(dev);
> >
> > +    s->fifo_trigger_handle = timer_new_ns(QEMU_CLOCK_VIRTUAL,
> > +                                          fifo_trigger_update, s);
> > +
> >       qemu_chr_fe_set_handlers(&s->chr, sifive_uart_can_rx, sifive_uart_rx,
> >                                sifive_uart_event, sifive_uart_be_change, s,
> >                                NULL, true);
> > @@ -206,12 +272,19 @@ static void sifive_uart_realize(DeviceState *dev, 
> > Error **errp)
> >   static void sifive_uart_reset_enter(Object *obj, ResetType type)
> >   {
> >       SiFiveUARTState *s = SIFIVE_UART(obj);
> > +
> > +    s->txfifo = 0;
> >       s->ie = 0;
> >       s->ip = 0;
> >       s->txctrl = 0;
> >       s->rxctrl = 0;
> >       s->div = 0;
> > +
> > +    s->tx_level = 0;
> >       s->rx_fifo_len = 0;
> > +
> > +    memset(s->rx_fifo, 0, SIFIVE_UART_RX_FIFO_SIZE);
> > +    memset(s->tx_fifo, 0, SIFIVE_UART_TX_FIFO_SIZE);
> >   }
> >
> >   static void sifive_uart_reset_hold(Object *obj, ResetType type)
>
> Have you considered using a Fifo8 here? This avoids having to manually roll 
> your own
> FIFO implementation.

Yeah, I will convert it to a Fifo8.

Alistair

>
>
> ATB,
>
> Mark.
>