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[PATCH v3 09/17] bsd-user: Add RISC-V thread setup and initialization su
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From: |
Ajeet Singh |
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Subject: |
[PATCH v3 09/17] bsd-user: Add RISC-V thread setup and initialization support |
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Date: |
Sat, 24 Aug 2024 14:56:27 +1000 |
From: Mark Corbin <mark@dibsco.co.uk>
Implemented functions for setting up and initializing threads in the
RISC-V architecture.
The 'target_thread_set_upcall' function sets up the stack pointer,
program counter, and function argument for new threads.
The 'target_thread_init' function initializes thread registers based on
the provided image information.
Signed-off-by: Mark Corbin <mark@dibsco.co.uk>
Signed-off-by: Ajeet Singh <itachis@FreeBSD.org>
Co-authored-by: Jessica Clarke <jrtc27@jrtc27.com>
Co-authored-by: Kyle Evans <kevans@FreeBSD.org>
---
bsd-user/riscv/target_arch_thread.h | 47 +++++++++++++++++++++++++++++
1 file changed, 47 insertions(+)
create mode 100644 bsd-user/riscv/target_arch_thread.h
diff --git a/bsd-user/riscv/target_arch_thread.h
b/bsd-user/riscv/target_arch_thread.h
new file mode 100644
index 0000000000..db0f9eb52c
--- /dev/null
+++ b/bsd-user/riscv/target_arch_thread.h
@@ -0,0 +1,47 @@
+/*
+ * RISC-V thread support
+ *
+ * Copyright (c) 2019 Mark Corbin
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef TARGET_ARCH_THREAD_H
+#define TARGET_ARCH_THREAD_H
+
+/* Compare with cpu_set_upcall() in riscv/riscv/vm_machdep.c */
+static inline void target_thread_set_upcall(CPURISCVState *regs,
+ abi_ulong entry, abi_ulong arg, abi_ulong stack_base,
+ abi_ulong stack_size)
+{
+ abi_ulong sp;
+
+ sp = ROUND_DOWN(stack_base + stack_size,16);
+
+ regs->gpr[xSP] = sp;
+ regs->pc = entry;
+ regs->gpr[xA0] = arg;
+}
+
+/* Compare with exec_setregs() in riscv/riscv/machdep.c */
+static inline void target_thread_init(struct target_pt_regs *regs,
+ struct image_info *infop)
+{
+ regs->sepc = infop->entry;
+ regs->regs[xRA] = infop->entry;
+ regs->regs[xA0] = infop->start_stack;
+ regs->regs[xSP] = ROUND_DOWN(infop->start_stack,16);
+}
+
+#endif /* TARGET_ARCH_THREAD_H */
--
2.34.1
- [PATCH v3 01/17] bsd-user: Implement RISC-V CPU initialization and main loop, (continued)
- [PATCH v3 01/17] bsd-user: Implement RISC-V CPU initialization and main loop, Ajeet Singh, 2024/08/24
- [PATCH v3 02/17] bsd-user: Add RISC-V CPU execution loop and syscall handling, Ajeet Singh, 2024/08/24
- [PATCH v3 03/17] bsd-user: Implement RISC-V CPU register cloning and reset functions, Ajeet Singh, 2024/08/24
- [PATCH v3 04/17] bsd-user: Implement RISC-V TLS register setup, Ajeet Singh, 2024/08/24
- [PATCH v3 05/17] bsd-user: Add RISC-V ELF definitions and hardware capability detection, Ajeet Singh, 2024/08/24
- [PATCH v3 06/17] bsd-user: Define RISC-V register structures and register copying, Ajeet Singh, 2024/08/24
- [PATCH v3 08/17] bsd-user: Implement RISC-V sysarch system call emulation, Ajeet Singh, 2024/08/24
- [PATCH v3 07/17] bsd-user: Add RISC-V signal trampoline setup function, Ajeet Singh, 2024/08/24
- [PATCH v3 09/17] bsd-user: Add RISC-V thread setup and initialization support,
Ajeet Singh <=
- [PATCH v3 10/17] bsd-user: Define RISC-V VM parameters and helper functions, Ajeet Singh, 2024/08/24
- [PATCH v3 11/17] bsd-user: Define RISC-V system call structures and constants, Ajeet Singh, 2024/08/24
- [PATCH v3 12/17] bsd-user: Add generic RISC-V64 target definitions, Ajeet Singh, 2024/08/24
- [PATCH v3 13/17] bsd-user: Define RISC-V signal handling structures and constants, Ajeet Singh, 2024/08/24
- [PATCH v3 14/17] bsd-user: Implement RISC-V signal trampoline setup functions, Ajeet Singh, 2024/08/24
- [PATCH v3 15/17] bsd-user: Implement 'get_mcontext' for RISC-V, Ajeet Singh, 2024/08/24
- [PATCH v3 16/17] bsd-user: Implement set_mcontext and get_ucontext_sigreturn for RISCV, Ajeet Singh, 2024/08/24
- [PATCH v3 17/17] bsd-user: Add RISC-V 64-bit Target Configuration and Debug XML Files, Ajeet Singh, 2024/08/24