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[PATCH v10 10/21] target/riscv: Expose zicfilp extension as a cpu proper
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From: |
Deepak Gupta |
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Subject: |
[PATCH v10 10/21] target/riscv: Expose zicfilp extension as a cpu property |
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Date: |
Tue, 27 Aug 2024 16:18:54 -0700 |
Signed-off-by: Deepak Gupta <debug@rivosinc.com>
---
target/riscv/cpu.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 2d031e3e74..8e1f05e5b1 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -1476,6 +1476,7 @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = {
/* Defaults for standard extensions */
MULTI_EXT_CFG_BOOL("sscofpmf", ext_sscofpmf, false),
MULTI_EXT_CFG_BOOL("zifencei", ext_zifencei, true),
+ MULTI_EXT_CFG_BOOL("zicfilp", ext_zicfilp, false),
MULTI_EXT_CFG_BOOL("zicsr", ext_zicsr, true),
MULTI_EXT_CFG_BOOL("zihintntl", ext_zihintntl, true),
MULTI_EXT_CFG_BOOL("zihintpause", ext_zihintpause, true),
--
2.44.0
- [PATCH v10 02/21] linux-user/riscv: set priv for qemu-user and defaults for *envcfg, (continued)
- [PATCH v10 02/21] linux-user/riscv: set priv for qemu-user and defaults for *envcfg, Deepak Gupta, 2024/08/27
- [PATCH v10 06/21] target/riscv: additional code information for sw check, Deepak Gupta, 2024/08/27
- [PATCH v10 01/21] target/riscv: expose *envcfg csr and priv to qemu-user as well, Deepak Gupta, 2024/08/27
- [PATCH v10 08/21] target/riscv: zicfilp `lpad` impl and branch tracking, Deepak Gupta, 2024/08/27
- [PATCH v10 04/21] target/riscv: Introduce elp state and enabling controls for zicfilp, Deepak Gupta, 2024/08/27
- [PATCH v10 11/21] target/riscv: Add zicfiss extension, Deepak Gupta, 2024/08/27
- [PATCH v10 09/21] disas/riscv: enable `lpad` disassembly, Deepak Gupta, 2024/08/27
- [PATCH v10 10/21] target/riscv: Expose zicfilp extension as a cpu property,
Deepak Gupta <=
- [PATCH v10 07/21] target/riscv: tracking indirect branches (fcfi) for zicfilp, Deepak Gupta, 2024/08/27
- [PATCH v10 13/21] target/riscv: tb flag for shadow stack instructions, Deepak Gupta, 2024/08/27
- [PATCH v10 17/21] target/riscv: implement zicfiss instructions, Deepak Gupta, 2024/08/27
- [PATCH v10 12/21] target/riscv: introduce ssp and enabling controls for zicfiss, Deepak Gupta, 2024/08/27
- [PATCH v10 20/21] disas/riscv: enable disassembly for compressed sspush/sspopchk, Deepak Gupta, 2024/08/27
- [PATCH v10 14/21] target/riscv: mmu changes for zicfiss shadow stack protection, Deepak Gupta, 2024/08/27
- [PATCH v10 15/21] target/riscv: AMO operations always raise store/AMO fault, Deepak Gupta, 2024/08/27
- [PATCH v10 16/21] target/riscv: update `decode_save_opc` to store extra word2, Deepak Gupta, 2024/08/27
- [PATCH v10 18/21] target/riscv: compressed encodings for sspush and sspopchk, Deepak Gupta, 2024/08/27