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Re: [PATCH v10 02/21] linux-user/riscv: set priv for qemu-user and defau
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From: |
Alistair Francis |
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Subject: |
Re: [PATCH v10 02/21] linux-user/riscv: set priv for qemu-user and defaults for *envcfg |
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Date: |
Wed, 28 Aug 2024 10:10:44 +1000 |
On Wed, Aug 28, 2024 at 9:20 AM Deepak Gupta <debug@rivosinc.com> wrote:
>
> set priv to be PRV_U for qemu-user on riscv. And set default value for
> *envcfg CSR.
>
> Signed-off-by: Deepak Gupta <debug@rivosinc.com>
You can probably just squash this with the previous patch
> ---
> linux-user/riscv/cpu_loop.c | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/linux-user/riscv/cpu_loop.c b/linux-user/riscv/cpu_loop.c
> index 52c49c2e42..7a68e8717b 100644
> --- a/linux-user/riscv/cpu_loop.c
> +++ b/linux-user/riscv/cpu_loop.c
> @@ -32,6 +32,10 @@ void cpu_loop(CPURISCVState *env)
> int trapnr;
> target_ulong ret;
>
> + env->priv = PRV_U;
> + env->senvcfg = 0;
> + env->menvcfg = 0;
I don't think this is the right place.
This should be handled by a CPU reset, which is still called for linux
user mode.
Alistair
> +
> for (;;) {
> cpu_exec_start(cs);
> trapnr = cpu_exec(cs);
> --
> 2.44.0
>
>
- [PATCH v10 00/21] riscv support for control flow integrity extensions, Deepak Gupta, 2024/08/27
- [PATCH v10 06/21] target/riscv: additional code information for sw check, Deepak Gupta, 2024/08/27
- [PATCH v10 01/21] target/riscv: expose *envcfg csr and priv to qemu-user as well, Deepak Gupta, 2024/08/27
- [PATCH v10 08/21] target/riscv: zicfilp `lpad` impl and branch tracking, Deepak Gupta, 2024/08/27
- [PATCH v10 04/21] target/riscv: Introduce elp state and enabling controls for zicfilp, Deepak Gupta, 2024/08/27
- [PATCH v10 11/21] target/riscv: Add zicfiss extension, Deepak Gupta, 2024/08/27
- [PATCH v10 09/21] disas/riscv: enable `lpad` disassembly, Deepak Gupta, 2024/08/27