[PATCH v2 12/14] tcg/riscv: Implement vector shs/v ops

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[PATCH v2 12/14] tcg/riscv: Implement vector shs/v ops

From:	LIU Zhiwei
Subject:	[PATCH v2 12/14] tcg/riscv: Implement vector shs/v ops
Date:	Fri, 30 Aug 2024 14:16:05 +0800

From: TANG Tiancheng <tangtiancheng.ttc@alibaba-inc.com>

Signed-off-by: TANG Tiancheng <tangtiancheng.ttc@alibaba-inc.com>
Reviewed-by: Liu Zhiwei <zhiwei_liu@linux.alibaba.com>
---
 tcg/riscv/tcg-target-con-set.h |  1 +
 tcg/riscv/tcg-target.c.inc     | 44 ++++++++++++++++++++++++++++++++++
 tcg/riscv/tcg-target.h         |  4 ++--
 3 files changed, 47 insertions(+), 2 deletions(-)

diff --git a/tcg/riscv/tcg-target-con-set.h b/tcg/riscv/tcg-target-con-set.h
index 6c9ad5188b..3154fe8ea8 100644
--- a/tcg/riscv/tcg-target-con-set.h
+++ b/tcg/riscv/tcg-target-con-set.h
@@ -29,3 +29,4 @@ C_O1_I1(v, v)
 C_O1_I2(v, v, v)
 C_O1_I2(v, v, vi)
 C_O1_I2(v, v, vK)
+C_O1_I2(v, v, r)
diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc
index 7de2da3571..31e161c5bc 100644
--- a/tcg/riscv/tcg-target.c.inc
+++ b/tcg/riscv/tcg-target.c.inc
@@ -357,6 +357,13 @@ typedef enum {
     OPC_VMSGT_VI = 0x7c000057 | V_OPIVI,
     OPC_VMSGT_VX = 0x7c000057 | V_OPIVX,
 
+    OPC_VSLL_VV = 0x94000057 | V_OPIVV,
+    OPC_VSLL_VX = 0x94000057 | V_OPIVX,
+    OPC_VSRL_VV = 0xa0000057 | V_OPIVV,
+    OPC_VSRL_VX = 0xa0000057 | V_OPIVX,
+    OPC_VSRA_VV = 0xa4000057 | V_OPIVV,
+    OPC_VSRA_VX = 0xa4000057 | V_OPIVX,
+
     OPC_VMV_V_V = 0x5e000057 | V_OPIVV,
     OPC_VMV_V_I = 0x5e000057 | V_OPIVI,
     OPC_VMV_V_X = 0x5e000057 | V_OPIVX,
@@ -2446,6 +2453,30 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
         riscv_set_vec_config_vl_vece(s, type, vece);
         tcg_out_opc_vv(s, OPC_VMINU_VV, a0, a1, a2, true);
         break;
+    case INDEX_op_shls_vec:
+        riscv_set_vec_config_vl_vece(s, type, vece);
+        tcg_out_opc_vx(s, OPC_VSLL_VX, a0, a1, a2, true);
+        break;
+    case INDEX_op_shrs_vec:
+        riscv_set_vec_config_vl_vece(s, type, vece);
+        tcg_out_opc_vx(s, OPC_VSRL_VX, a0, a1, a2, true);
+        break;
+    case INDEX_op_sars_vec:
+        riscv_set_vec_config_vl_vece(s, type, vece);
+        tcg_out_opc_vx(s, OPC_VSRA_VX, a0, a1, a2, true);
+        break;
+    case INDEX_op_shlv_vec:
+        riscv_set_vec_config_vl_vece(s, type, vece);
+        tcg_out_opc_vv(s, OPC_VSLL_VV, a0, a1, a2, true);
+        break;
+    case INDEX_op_shrv_vec:
+        riscv_set_vec_config_vl_vece(s, type, vece);
+        tcg_out_opc_vv(s, OPC_VSRL_VV, a0, a1, a2, true);
+        break;
+    case INDEX_op_sarv_vec:
+        riscv_set_vec_config_vl_vece(s, type, vece);
+        tcg_out_opc_vv(s, OPC_VSRA_VV, a0, a1, a2, true);
+        break;
     case INDEX_op_rvv_cmp_vx:
         riscv_set_vec_config_vl_vece(s, type, vece);
         tcg_out_cmp_vec_vx(s, a2, a0, a1);
@@ -2583,6 +2614,12 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, 
unsigned vece)
     case INDEX_op_smin_vec:
     case INDEX_op_umax_vec:
     case INDEX_op_umin_vec:
+    case INDEX_op_shls_vec:
+    case INDEX_op_shrs_vec:
+    case INDEX_op_sars_vec:
+    case INDEX_op_shlv_vec:
+    case INDEX_op_shrv_vec:
+    case INDEX_op_sarv_vec:
         return 1;
     case INDEX_op_cmp_vec:
         return -1;
@@ -2753,7 +2790,14 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode 
op)
     case INDEX_op_smin_vec:
     case INDEX_op_umax_vec:
     case INDEX_op_umin_vec:
+    case INDEX_op_shlv_vec:
+    case INDEX_op_shrv_vec:
+    case INDEX_op_sarv_vec:
         return C_O1_I2(v, v, v);
+    case INDEX_op_shls_vec:
+    case INDEX_op_shrs_vec:
+    case INDEX_op_sars_vec:
+        return C_O1_I2(v, v, r);
     case INDEX_op_rvv_merge_vec:
         return C_O1_I2(v, v, vK);
     case INDEX_op_rvv_cmp_vi:
diff --git a/tcg/riscv/tcg-target.h b/tcg/riscv/tcg-target.h
index 35e7086ad7..41c6c446e8 100644
--- a/tcg/riscv/tcg-target.h
+++ b/tcg/riscv/tcg-target.h
@@ -158,8 +158,8 @@ typedef enum {
 #define TCG_TARGET_HAS_rots_vec         0
 #define TCG_TARGET_HAS_rotv_vec         0
 #define TCG_TARGET_HAS_shi_vec          0
-#define TCG_TARGET_HAS_shs_vec          0
-#define TCG_TARGET_HAS_shv_vec          0
+#define TCG_TARGET_HAS_shs_vec          1
+#define TCG_TARGET_HAS_shv_vec          1
 #define TCG_TARGET_HAS_mul_vec          1
 #define TCG_TARGET_HAS_sat_vec          1
 #define TCG_TARGET_HAS_minmax_vec       1
-- 
2.43.0

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[PATCH v2 02/14] util: Add RISC-V vector extension probe in cpuinfo, (continued)
- [PATCH v2 02/14] util: Add RISC-V vector extension probe in cpuinfo, LIU Zhiwei, 2024/08/30
- [PATCH v2 03/14] tcg/riscv: Add basic support for vector, LIU Zhiwei, 2024/08/30
- [PATCH v2 04/14] tcg/riscv: Add riscv vset{i}vli support, LIU Zhiwei, 2024/08/30
- [PATCH v2 05/14] tcg/riscv: Implement vector load/store, LIU Zhiwei, 2024/08/30
- [PATCH v2 06/14] tcg/riscv: Implement vector mov/dup{m/i}, LIU Zhiwei, 2024/08/30
- [PATCH v2 07/14] tcg/riscv: Add support for basic vector opcodes, LIU Zhiwei, 2024/08/30
- [PATCH v2 08/14] tcg/riscv: Implement vector cmp ops, LIU Zhiwei, 2024/08/30
- [PATCH v2 09/14] tcg/riscv: Implement vector neg ops, LIU Zhiwei, 2024/08/30
- [PATCH v2 10/14] tcg/riscv: Implement vector sat/mul ops, LIU Zhiwei, 2024/08/30
- [PATCH v2 11/14] tcg/riscv: Implement vector min/max ops, LIU Zhiwei, 2024/08/30
- [PATCH v2 12/14] tcg/riscv: Implement vector shs/v ops, LIU Zhiwei <=
- [PATCH v2 13/14] tcg/riscv: Implement vector roti/v/x shi ops, LIU Zhiwei, 2024/08/30
- [PATCH v2 14/14] tcg/riscv: Enable native vector support for TCG host, LIU Zhiwei, 2024/08/30

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