Re: [PATCH v2 0/9] riscv: Add support for MIPS P8700 CPU

[Alistair Francis]

On Mon, Jun 2, 2025 at 11:14 PM Djordje Todorovic
<Djordje.Todorovic@htecgroup.com> wrote:
>
> Several things implemented in v2:
>   - Addressing review comments
>     - Simplify `target/riscv/xmips.decode`
>   - Rebase on top of latest master
>   - Fix code format
>
> Djordje Todorovic (9):
>   hw/intc: Allow gaps in hartids for aclint and aplic
>   target/riscv: Add cpu_set_exception_base
>   target/riscv: Add MIPS P8700 CPU
>   target/riscv: Add MIPS P8700 CSRs
>   target/riscv: Add mips.ccmov instruction
>   target/riscv: Add mips.pref instruction
>   target/riscv: Add Xmipslsp instructions
>   configs/devices: Add MIPS Boston-aia board model to RISC-V
>   hw/riscv: Add a network device e1000e to the boston-aia

Thanks for the patches! There are now some review comments (sorry for
the delay), please send a v3 once they have been addressed

Alistair

>
>  configs/devices/riscv64-softmmu/default.mak |   1 +
>  hw/intc/riscv_aclint.c                      |  33 +-
>  hw/intc/riscv_aplic.c                       |  10 +-
>  hw/misc/Kconfig                             |   5 +
>  hw/misc/meson.build                         |   1 +
>  hw/misc/riscv_cmgcr.c                       | 204 ++++++++
>  hw/misc/riscv_cpc.c                         | 225 +++++++++
>  hw/pci/pci.c                                |  15 +-
>  hw/riscv/Kconfig                            |   6 +
>  hw/riscv/boston-aia.c                       | 489 ++++++++++++++++++++
>  hw/riscv/cps.c                              | 187 ++++++++
>  hw/riscv/meson.build                        |   1 +
>  include/hw/misc/riscv_cmgcr.h               |  77 +++
>  include/hw/misc/riscv_cpc.h                 |  69 +++
>  include/hw/riscv/cps.h                      |  75 +++
>  target/riscv/cpu-qom.h                      |   1 +
>  target/riscv/cpu.c                          |  28 ++
>  target/riscv/cpu.h                          |   9 +
>  target/riscv/cpu_cfg.h                      |   5 +
>  target/riscv/cpu_cfg_fields.h.inc           |   3 +
>  target/riscv/insn_trans/trans_xmips.c.inc   | 137 ++++++
>  target/riscv/meson.build                    |   2 +
>  target/riscv/mips_csr.c                     | 219 +++++++++
>  target/riscv/translate.c                    |  11 +
>  target/riscv/xmips.decode                   |  35 ++
>  25 files changed, 1837 insertions(+), 11 deletions(-)
>  create mode 100644 hw/misc/riscv_cmgcr.c
>  create mode 100644 hw/misc/riscv_cpc.c
>  create mode 100644 hw/riscv/boston-aia.c
>  create mode 100644 hw/riscv/cps.c
>  create mode 100644 include/hw/misc/riscv_cmgcr.h
>  create mode 100644 include/hw/misc/riscv_cpc.h
>  create mode 100644 include/hw/riscv/cps.h
>  create mode 100644 target/riscv/insn_trans/trans_xmips.c.inc
>  create mode 100644 target/riscv/mips_csr.c
>  create mode 100644 target/riscv/xmips.decode
>
> --
> 2.34.1
>