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Re: [Qemu-ppc] [Qemu-devel] [PATCH 05/58] PPC: Add CPU local MMIO region

From: Peter Maydell
Subject: Re: [Qemu-ppc] [Qemu-devel] [PATCH 05/58] PPC: Add CPU local MMIO regions to MPIC
Date: Wed, 14 Sep 2011 11:07:31 +0100

On 14 September 2011 09:42, Alexander Graf <address@hidden> wrote:
> The MPIC exports a register set for each CPU connected to it. They can all
> be accessed through specific registers or using a shadow page that is mapped
> differently depending on which CPU accesses it.
> This patch implements the shadow map, making it possible for guests to access
> the CPU local registers using the same address on each CPU.

> +static int get_current_cpu(void)
> +{
> +  return cpu_single_env->cpu_index;
> +}

This is the standard way of doing this (we use it on ARM as well), but
it's pretty clearly a hack. "which master sent this memory transaction"
is an attribute that ought to be passed down to the MMIO read/write
functions, really (along with other interesting things like "priv or
not?" and probably architecture specific attributes like ARM's
"secure/non-secure"); this matches how hardware does it where the
attributes are passed along as extra signals in the bus fabric.
(Sometimes hardware also does this by having buses from the different
cores be totally separate paths at the point where this kind of device
is connected, before merging together later; we don't really support
modelling that either :-))

Not a nak, just an observation while I'm thinking about it.

-- PMM

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