[Top][All Lists]

[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

Re: [Qemu-ppc] qemu-kvm: Role of flush_icache_range on PPC

From: Benjamin Herrenschmidt
Subject: Re: [Qemu-ppc] qemu-kvm: Role of flush_icache_range on PPC
Date: Thu, 29 Sep 2011 07:02:35 +1000

On Wed, 2011-09-28 at 12:27 -0500, Scott Wood wrote:

> Why would it need to be synchronous?  Even if it's asynchronous emulated
> DMA, we don't want it sitting around only in a data cache that
> instruction fetches won't snoop.

Except that this is exactly what happens on real HW :-)

The guest will do the necessary invalidations. DMA doesn't keep the
icache coherent on HW, why should it on kvm/qemu ?

> It's not implemented yet in mainline for powerpc (we have something
> internal that is on the backlog of things to be cleaned up and sent
> out), but this is what we'd do for kvm_arch_insert_sw_breakpoint().

Yes, breakpoints do need a flash, as does the initial program load.


reply via email to

[Prev in Thread] Current Thread [Next in Thread]