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Re: [Qemu-ppc] [Qemu-devel] [PATCH 20/22] ppc: move load and store helpe

From: Alexander Graf
Subject: Re: [Qemu-ppc] [Qemu-devel] [PATCH 20/22] ppc: move load and store helpers, switch to AREG0 free mode
Date: Wed, 02 May 2012 15:00:21 +0200
User-agent: Mozilla/5.0 (X11; Linux x86_64; rv:10.0.3) Gecko/20120306 Thunderbird/10.0.3

On 04/30/2012 05:34 PM, malc wrote:
On Mon, 30 Apr 2012, Alexander Graf wrote:

On 30.04.2012, at 12:45, Alexander Graf wrote:

On 22.04.2012, at 15:26, Blue Swirl wrote:

Add an explicit CPUPPCState parameter instead of relying on AREG0
and rename op_helper.c (which only contains load and store helpers)
to mem_helper.c. Remove AREG0 swapping in

Switch to AREG0 free mode. Use cpu_ld{l,uw}_code in translation
and interrupt handling, cpu_{ld,st}{l,uw}_data in loads and stores.
This patch breaks qemu-system-ppc64 on ppc32 host user space for me. I'm trying 
to debug it down, but worst case I'll omit this patch set for 1.1.
Ok, so apparently nobody ever tested TCG_AREG0 mode with the ppc tcg
target. It looks as if the
64-bit-guest-registers-in-32-bit-host-registers code path is missing

This actually makes me less confident that this is a change we want for
1.1. I'll remove the patches from the queue.


TCG register swizzling code:

     /* XXX/FIXME: suboptimal */
     tcg_out_mov(s, TCG_TYPE_I32, tcg_target_call_iarg_regs[3],
     tcg_out_mov(s, TCG_TYPE_I64, tcg_target_call_iarg_regs[2],
     tcg_out_mov(s, TCG_TYPE_TL, tcg_target_call_iarg_regs[1],
     tcg_out_mov(s, TCG_TYPE_PTR, tcg_target_call_iarg_regs[0],
     tcg_out_call (s, (tcg_target_long) qemu_st_helpers[opc], 1);

The above snippet is incorrect for SysV ppc32 ABI, due to misalignment
of long long argument in register file.

Hmm - so what would be the correct version? :)


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