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Re: [Qemu-ppc] [Qemu-devel] [PATCH for-1.1 3/3] tcg/ppc: Fix CONFIG_TCG_

From: Alexander Graf
Subject: Re: [Qemu-ppc] [Qemu-devel] [PATCH for-1.1 3/3] tcg/ppc: Fix CONFIG_TCG_PASS_AREG0 mode
Date: Tue, 8 May 2012 20:20:39 +0200

On 08.05.2012, at 19:43, Alexander Graf wrote:

> On 08.05.2012, at 19:39, Alexander Graf wrote:
>> On 07.05.2012, at 01:46, Andreas Färber wrote:
>>> Adjust the tcg_out_qemu_{ld,st}() slow paths to pass AREG0 in r3.
>>> Automate the register numbering to avoid double-coding the two modes,
>>> and introduce TCG_TARGET_CALL_ALIGN_I64_ARG() macro to align for SVR4
>>> but not for Darwin ABI.
>>> Based on patch by malc.
>> AREG0-free PPC works for me with this patch on a ppc32 host.
>> Tested-by: Alexander Graf <address@hidden>
> I take that one back - it breaks once things get more complex. Debugging ...

I have no idea how this code could have ever worked. We are getting unknown 
register numbers as input variables. Then mr them into our C ABI parameter 
registers (r3+). Then we call the C helper to do the load/store for us.

Now, what if one of those input parameters is within r3-r7 (which is the 
highest register passed into the C ld function)? We'd happily do something like

  mr r3, r5
  mr r4, r3
  mr r5, ...

at which point we have long overwritten the actual value of r3!

The following patch on top of Andreas' patch makes ppc32 tcg work for me. I'd 
suggest committing his patch + the one below to have a working rc1 and take it 
from there.


diff --git a/tcg/ppc/tcg-target.c b/tcg/ppc/tcg-target.c
index ace5548..917bc39 100644
--- a/tcg/ppc/tcg-target.c
+++ b/tcg/ppc/tcg-target.c
@@ -116,11 +116,13 @@ static const int tcg_target_reg_alloc_order[] = {
 #ifdef _CALL_DARWIN
+#if 0

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