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Re: [Qemu-ppc] Qemu pSeries AIX ADB boot

From: Michael Sabino
Subject: Re: [Qemu-ppc] Qemu pSeries AIX ADB boot
Date: Mon, 11 Jun 2012 21:37:05 -0500

I'm not sure why when I type "info registers" a register called NIP is cycling through several different values and reaching the same point at times. some other registers also seem to be changing.

0x000000000095e7a4:  cmpwi   r3,0
0x000000000095e7a8:  beq+    0x95e7a0

0x000000000095e7a0:  bl      0x1e5be0

That is the last thing I see in the instruction log after putting in some generic spr's and applying the PPP code below.

I don't get any more invalid spr's after I edited translate_init.c.

Here is some sPAPR pSeries Partition Pool code that I think is better than the version in the aix qemu tree. It seems to compile, but it does not get me any further as far as I can tell.

It's based on the suggestion of Alex to look at http://lxr.free-electrons.com/source/arch/powerpc/kernel/lparcfg.c?a=m68k#L108.

static target_ulong h_get_ppp(CPUPPCState *env, sPAPREnvironment *spapr,
                              target_ulong opcode, target_ulong *args)
    printf("\nh_get_ppp might not be right yet\n");
    env->gpr[4] = 100; // Processor capacity percentage
    env->gpr[5] = 0; // Unallocated processor capacity percentage

    int group_num  = 1; // Group number
    int pool_num = 1; // Pool number

    ulong r6_bitmask = ((group_num & 0xffff) << 2*8) + ((pool_num & 0xffff)); // bitmask for r6
    env->gpr[6] = r6_bitmask;

    bool capped = 1; // Capped
    int weight = 128; // Capacity weight
    int unallocated_weight = 0; // // Unallocated Variable Processor Capacity Weight
    int active_procs_in_pool = 1; // Active processors in Physical Processor Pool
    int active_system_procs = 1; // Processors active on platform

    target_ulong r7_bitmask1 = (((target_ulong)capped & 0x01) << 6*8) + (((target_ulong)weight & 0xff) << 5*8) + (((target_ulong)unallocated_weight & 0xff) << 4*8);

    ulong r7_bitmask2 = ((active_procs_in_pool & 0xffff) << 2*8) + (active_system_procs & (0xffff));
    env->gpr[7] = r7_bitmask2 + r7_bitmask1;
    int phys_platform_procs = 1; // Physical platform procs allocated to virtualization
    int max_proc_cap_avail = 100; // Max procs capacity % available to the partitions pool.
    int entitled_proc_cap_avail = 100; // Entitled procs capacity % available to the partitions pool
    target_ulong r8_bitmask1 = ((target_ulong)phys_platform_procs << 6*8);
    ulong r8_bitmask2 =  ((max_proc_cap_avail & 0xffffff) << 3*8) + ((entitled_proc_cap_avail & 0xffffff));
    env->gpr[8] = r8_bitmask1 + r8_bitmask2;
    return H_SUCCESS;

I'm not sure what variables in the env block would be useful for the above code yet.


Michael Sabino

On Mon, Jun 11, 2012 at 5:35 PM, Alexander Graf <address@hidden> wrote:

On 11.06.2012, at 21:12, Michael Sabino wrote:

> Actually, the POWER7 code seems to get further than the 970 in this case with the exception handling code disabled.
> As far as the code with the exception handling code enabled -
> I added the spr's, but an invalid program exception seems to be being generated which doesn't relate to the writing/reading invalid SPR. I'm not sure what it's origin is quite yet. Any ideas for figuring this out?

-d in_asm should be able to tell you in /tmp/qemu.log after you ran into it :)


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