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Re: [Qemu-ppc] [RFC PATCH 05/17] KVM: PPC: booke: Extend MAS2 EPN mask f

From: Alexander Graf
Subject: Re: [Qemu-ppc] [RFC PATCH 05/17] KVM: PPC: booke: Extend MAS2 EPN mask for 64-bit
Date: Wed, 4 Jul 2012 15:49:47 +0200

On 25.06.2012, at 14:26, Mihai Caraman wrote:

> Extend MAS2 EPN mask for 64-bit hosts, to retain most significant bits.
> Change get tlb eaddr to use this mask.

Please see section in the PowerISA 2.06b:

MMU behavior is largely unaffected by whether the thread is in 32-bit 
computation mode (MSRCM=0) or 64- bit computation mode (MSRCM=1). The only 
differ- ences occur in the EPN field of the TLB entry and the EPN field of 
MAS2. The differences are summarized here.

        •  Executing a tlbwe instruction in 32-bit mode will set bits 0:31 of 
the TLB EPN field to zero unless MAS0ATSEL is set, in which case those bits are 
not written to zero.
        •  In 32-bit implementations, MAS2U can be used to read or write 
EPN0:31 of MAS2.

So if MSR.CM is not set tlbwe should mask the upper 32 bits out - which can 
happen regardless of CONFIG_64BIT.
Also, we need to implement MAS2U, to potentially make the upper 32bits of MAS2 
available, right? But that one isn't as important as the first bit.


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