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Re: [Qemu-ppc] [PATCH] openpic: Added BRR1 register

From: Alexander Graf
Subject: Re: [Qemu-ppc] [PATCH] openpic: Added BRR1 register
Date: Mon, 16 Jul 2012 16:55:22 +0200
User-agent: Mozilla/5.0 (X11; Linux x86_64; rv:10.0.3) Gecko/20120306 Thunderbird/10.0.3

On 07/12/2012 01:07 PM, Bharat Bhushan wrote:
Linux mpic driver uses (changes may be in pipeline to get upstreamed soon)
BRR1. This patch adds the support to emulate readonly BRR1.

Signed-off-by: Bharat Bhushan<address@hidden>
  hw/openpic.c |    6 ++++++
  1 files changed, 6 insertions(+), 0 deletions(-)

diff --git a/hw/openpic.c b/hw/openpic.c
index 58ef871..244155b 100644
--- a/hw/openpic.c
+++ b/hw/openpic.c
@@ -595,6 +595,8 @@ static void openpic_gbl_write (void *opaque, 
target_phys_addr_t addr, uint32_t v
      if (addr&  0xF)
      switch (addr) {
+    case 0x00: /* BRR1 Readonly */
+        break;
      case 0x40:
      case 0x50:
      case 0x60:
@@ -671,6 +673,7 @@ static uint32_t openpic_gbl_read (void *opaque, 
target_phys_addr_t addr)
      case 0x1090: /* PINT */
          retval = 0x00000000;
+    case 0x00:

Add a comment saying what register this is. We really should be using #define's here, but it would be even worse to have it converted only half-way, so just stick with the comment for now.

      case 0x40:
      case 0x50:
      case 0x60:
@@ -893,6 +896,9 @@ static uint32_t openpic_cpu_read_internal(void *opaque, 
target_phys_addr_t addr,
      dst =&opp->dst[idx];
      addr&= 0xFF0;
      switch (addr) {
+    case 0x00: /* BRR1 */
+        retval = 0x00400200;

Please unmagicify this one :)


+        break;
      case 0x80: /* PCTP */
          retval = dst->pctp;

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