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Re: [Qemu-ppc] [Qemu-devel] [PATCH 10/40] Adding BAR0 for e500 PCI contr

From: Andreas Färber
Subject: Re: [Qemu-ppc] [Qemu-devel] [PATCH 10/40] Adding BAR0 for e500 PCI controller
Date: Fri, 14 Dec 2012 14:49:52 +0100
User-agent: Mozilla/5.0 (X11; Linux x86_64; rv:17.0) Gecko/17.0 Thunderbird/17.0

Am 14.12.2012 13:13, schrieb Alexander Graf:
> From: Bharat Bhushan <address@hidden>
> PCI Root complex have TYPE-1 configuration header while PCI endpoint
> have type-0 configuration header. The type-1 configuration header have
> a BAR (BAR0). In Freescale PCI controller BAR0 is used for mapping pci
> address space to CCSR address space. This can used for 2 purposes: 1)
> for MSI interrupt generation 2) Allow CCSR registers access when configured
> as PCI endpoint, which I am not sure is a use case with QEMU-KVM guest.
> What I observed is that when guest read the size of BAR0 of host controller
> configuration header (TYPE1 header) then it always reads it as 0. When
> looking into the QEMU hw/ppce500_pci.c, I do not find the PCI controller
> device registering BAR0. I do not find any other controller also doing so
> may they do not use BAR0.
> There are two issues when BAR0 is not there (which I can think of):
> 1) There should be BAR0 emulated for PCI Root complex (TYPE1 header) and
> when reading the size of BAR0, it should give size as per real h/w.
> 2) Do we need this BAR0 inbound address translation?
>         When BAR0 is of non-zero size then it will be configured for PCI
> address space to local address(CCSR) space translation on inbound access.
> The primary use case is for MSI interrupt generation. The device is
> configured with an address offsets in PCI address space, which will be
> translated to MSI interrupt generation MPIC registers. Currently I do
> not understand the MSI interrupt generation mechanism in QEMU and also
> IIRC we do not use QEMU MSI interrupt mechanism on e500 guest machines.
> But this BAR0 will be used when using MSI on e500.
> I can see one more issue, There are ATMUs emulated in hw/ppce500_pci.c,
> but i do not see these being used for address translation.
> So far that works because pci address space and local address space are 1:1
> mapped. BAR0 inbound translation + ATMU translation will complete the address
> translation of inbound traffic.
> Signed-off-by: Bharat Bhushan <address@hidden>
> [agraf: fix double variable assignment w/o read]
> Signed-off-by: Alexander Graf <address@hidden>

Reviewed-by: Andreas Färber <address@hidden>


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