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Re: [Qemu-ppc] [Qemu-devel] [PATCH] PPC: Introduce 32bit only cmp ops

From: Alexander Graf
Subject: Re: [Qemu-ppc] [Qemu-devel] [PATCH] PPC: Introduce 32bit only cmp ops
Date: Wed, 8 May 2013 12:38:22 +0200

On 08.05.2013, at 12:34, Torbjorn Granlund wrote:

> Aurelien Jarno <address@hidden> writes:
>  You have to declare the L bit as invalid, so that trying to execute a
>  64-bit cmp* instruction on a 32-bit CPU causes an invalid instruction
>  exception.
> Don't people read what I write?

At least on my e500mc machine I happen to have handy, the following instruction 
gives me an illegal instruction exception:

  10000320:     2f a0 00 00     cmpi    cr7,1,r0,0

So for 32bit CPU types we have to mark the L bit invalid which means we always 
get into the branches that take us to cmp32. For 64bit capable CPUs we 
obviously want to honor the L bit even when running in 32bit mode (MSR.SF=0), 
as that's what real CPUs do.


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