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Re: [Qemu-ppc] [Qemu-devel] [PATCH] PPC: Depend behavior of cmp instruct

From: Aurelien Jarno
Subject: Re: [Qemu-ppc] [Qemu-devel] [PATCH] PPC: Depend behavior of cmp instructions only on instruction encoding
Date: Wed, 8 May 2013 18:16:54 +0200
User-agent: Mutt/1.5.21 (2010-09-15)

On Wed, May 08, 2013 at 05:54:27PM +0200, Torbjorn Granlund wrote:
> Aurelien Jarno <address@hidden> writes:
>   As it seems you have good contact with IBM, could you please ask them
>   to fix their manuals?
> What flaw have your found?

Don't people read what I write? From one of my previous email:

Quoting the "IBM PowerPC Microprocessor Family: The Programming                 
Environments Manual for 32 and 64-bit Microprocessors":                         

| Note: In 32-bit implementations, if L = 1 the instruction form is invalid.

This doesn't match what your contact says.

>   At least Freescale CPUs match what IBM documentation says.
> Which ones?  Freescale 7447 and Freescale e500 disagree.  (Or at least
> some versions of these chips, perhaps newer e500 steppings ignore the L
> bit.)

The e500 CPU doesn't ignore the L bit, like the IBM manual says.

>   IBM CPUs don't.
> Which ones?

The one from your contact saying that reserved fields should be ignored
by hardware.

>   No it's not correct, it doesn't match neither Freescale nor IBM
>   behaviour. It also means the same code executed on a 32-bit emulated CPU
>   run with qemu-system-ppc will behave differently than when run with
>   qemu-system-ppc64. This is fine for now as we are in freeze period, but
>   should be fixed afterwards.
> I think one should check if it is a 64-bit CPU vs 32-bit CPU, as your
> patch did.  (If I read it correctly; while I am an expert in the area, I
> am very little familiar with qemu's innards.)  Except that it should
> probably not cast an exception (but I think either way there is no
> calamity).

Looking more into details about the issue. Old *PowerPC* manuals (the
one from the 7447 era) clearly states that the L bit must trigger an
invalid instruction exception.

*POWER* manuals states that reserved fields in instructions are ignored by
on Server environment, but not on Embedded environment, though it is now
phased-in on the latter.

In short everybody is correct, it only depends on the CPU.

Aurelien Jarno                          GPG: 1024D/F1BCDB73
address@hidden                 http://www.aurel32.net

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