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Re: [Qemu-ppc] [Qemu-devel] [PATCH 05/17] pseries: savevm support for XI

From: David Gibson
Subject: Re: [Qemu-ppc] [Qemu-devel] [PATCH 05/17] pseries: savevm support for XICS interrupt controller
Date: Tue, 9 Jul 2013 17:17:50 +1000
User-agent: Mutt/1.5.21 (2010-09-15)

On Mon, Jul 08, 2013 at 01:31:59PM -0500, Anthony Liguori wrote:
> Alexey Kardashevskiy <address@hidden> writes:
> > From: David Gibson <address@hidden>
> >  void xics_common_cpu_setup(struct icp_state *icp, PowerPCCPU *cpu)
> >  {
> >      CPUState *cs = CPU(cpu);
> > @@ -523,7 +578,11 @@ void xics_common_cpu_setup(struct icp_state *icp, 
> > PowerPCCPU *cpu)
> >  
> >  void xics_cpu_setup(struct icp_state *icp, PowerPCCPU *cpu)
> >  {
> > +    CPUState *cs = CPU(cpu);
> > +    struct icp_server_state *ss = &icp->ss[cs->cpu_index];
> > +
> >      xics_common_cpu_setup(icp, cpu);
> > +    vmstate_register(NULL, cs->cpu_index, &vmstate_icp_server, ss);
> This is an indication that something is wrong.
> You should tie the vmstate section to DeviceState::vmsd.  You only need
> to do this because you haven't converted everything to QOM yet.
> Please do that to avoid these hacks.

So, Alexey addressed the xics vs. xics-kvm issues.  But there's
another factor here.  It's not clear to me how you'd QOM this

What's being registered here is the "presentation server".  That's the
per-CPU part - vaguely equivalent to the LAPIC on x86.  x86 doesn't
have something equivalent here, because they register the LAPIC state
as part of the CPU state, but we can't do that because the ICP is not
bound to the CPU as tightly - a POWER7 using a different interrupt
architecture would certainly be possible.

So to do this with QOM, would the ICP need to be registered as a child
of the cpu object?

David Gibson                    | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au  | minimalist, thank you.  NOT _the_ _other_
                                | _way_ _around_!

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