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Re: [Qemu-ppc] [Qemu-devel] [PATCH] roms: Flush icache when writing roms

From: address@hidden
Subject: Re: [Qemu-ppc] [Qemu-devel] [PATCH] roms: Flush icache when writing roms to guest memory
Date: Wed, 11 Dec 2013 14:18:05 +0000

> -----Original Message-----
> From: Peter Maydell [mailto:address@hidden
> Sent: Wednesday, December 11, 2013 4:07 PM
> To: Alexander Graf
> Cc: Paolo Bonzini; Vlad Bogdan-BOGVLAD1; QEMU Developers; qemu-
> address@hidden; Sethi Varun-B16395; Wood Scott-B07421; Caraman Mihai
> Claudiu-B02008
> Subject: Re: [Qemu-devel] [PATCH] roms: Flush icache when writing roms to
> guest memory
> On 11 December 2013 13:35, Alexander Graf <address@hidden> wrote:
> > How would KVM know when things changed inside of a memory region?
> > It's up to user space to manage the contents of a memory region, no?
> If the architecture spec says that a freshly reset physical CPU has
> coherent icache and dcache, then resetting the vCPU should also
> ensure the icache and dcache are coherent, so one way to solve
> this would be just to make sure that vcpu reset did the right thing.

This is not related to reset operation. Freescale e500 core family
does not assure the coherency between data and instruction cache.
This is an extract from reference manual:

'When a processor modifies any memory location that can contain an
instruction, software must ensure that the instruction cache is made
consistent with data memory and that the modifications are made visible
to the instruction fetching mechanism. This must be done even if the
cache is disabled or if the page is marked caching-inhibited.'

So it's the loader duty to synchronize the instruction cache.


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