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Re: [Qemu-ppc] [PATCH v2 10/14] pci: allow 0 address for PCI IO regions

From: Michael S. Tsirkin
Subject: Re: [Qemu-ppc] [PATCH v2 10/14] pci: allow 0 address for PCI IO regions
Date: Thu, 12 Dec 2013 16:34:37 +0200

On Thu, Dec 05, 2013 at 11:33:48PM +0000, Peter Maydell wrote:
> On 5 December 2013 22:33, Michael Roth <address@hidden> wrote:
> > Some kernels program a 0 address for io regions. PCI 3.0 spec
> > sectio doesn't seem to disallow this.
> Hmm. The last PCI spec I looked at said 0 wasn't a valid MMIO
> address, so the variant of this patch I wrote a while back made it
> a per PCI device flag whether a particular device let you get away
> with it:
>  http://patchwork.ozlabs.org/patch/269133/
> (the device in question for me was the versatile-pci host bridge).
> And presumably whoever put that specific check for 0 into
> QEMU had a reason for it.

It used to be the case that if you created a conflicting
value for the BAR, you corrupted dispatch tables forever.
Now that dispatch tables are rebuilt on any change that
is less of an issue, but maybe that code is there to handle that,
e.g. to avoid conflictig with apic or other non pci devices.

> On the other hand I can't now find whatever document it was
> that I was reading that claimed 0 wasn't valid :-(
> thanks
> -- PMM

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