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Re: [Qemu-ppc] [PATCH] roms: Flush icache when writing roms to guest mem

From: Peter Maydell
Subject: Re: [Qemu-ppc] [PATCH] roms: Flush icache when writing roms to guest memory
Date: Sat, 14 Dec 2013 11:08:50 +0000

On 14 December 2013 10:58, Paolo Bonzini <address@hidden> wrote:
> Il 13/12/2013 20:18, Scott Wood ha scritto:
>>> Also are you sure flush_icache_range()
>>> works correctly when multiple threads (multiple vCPUs,
>>> potentially executing on different host CPUs) are involved?
>> On PPC these cache operations broadcast, and are the architecturally
>> defined way of doing self-modifying code.
> I expect that to be the same on any cache-coherent system.

On ARM you have the choice of "clean/invalidate sufficient to
run code on this CPU" vs "sufficient to run code on any CPU"
(the latter obviously is a more expensive operation). As it happens
I've checked through and the syscall/gcc primitive we use is
doing the latter not the former. But I did have to check.

I think SPARC is also OK (the manual defines the 'flush'
insn as working for all cpus). Haven't checked others.

-- PMM

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