Re: [Qemu-ppc] [PATCH 0/5] targe-ppc: 970/p5+/p7/p7+/p8 SPRs cleanup

qemu-ppc

[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

Re: [Qemu-ppc] [PATCH 0/5] targe-ppc: 970/p5+/p7/p7+/p8 SPRs cleanup

From:	Alexander Graf
Subject:	Re: [Qemu-ppc] [PATCH 0/5] targe-ppc: 970/p5+/p7/p7+/p8 SPRs cleanup
Date:	Fri, 20 Dec 2013 11:51:04 +0100

On 20.12.2013, at 07:41, Alexey Kardashevskiy <address@hidden> wrote:

> This removes not supported SPR from CPU classes.

Thanks a lot! Applied all to ppc-next.


Alex

[Prev in Thread]

Current Thread

[Next in Thread]

[Qemu-ppc] [PATCH 0/5] targe-ppc: 970/p5+/p7/p7+/p8 SPRs cleanup, Alexey Kardashevskiy, 2013/12/20
- [Qemu-ppc] [PATCH 1/5] target-ppc: fix LPCR SPR number, Alexey Kardashevskiy, 2013/12/20
- [Qemu-ppc] [PATCH 5/5] target-ppc: remove unsupported SPRs from 970 and P5+, Alexey Kardashevskiy, 2013/12/20
- [Qemu-ppc] [PATCH 3/5] target-ppc: fix SPR_CTRL/SPR_UCTRL register numbers, Alexey Kardashevskiy, 2013/12/20
- [Qemu-ppc] [PATCH 2/5] target-ppc: remove powerpc 970gx, Alexey Kardashevskiy, 2013/12/20
- [Qemu-ppc] [PATCH 4/5] target-ppc: remove embedded MMU SPRs from 970, P5+/7/7+/8, Alexey Kardashevskiy, 2013/12/20
- Re: [Qemu-ppc] [PATCH 0/5] targe-ppc: 970/p5+/p7/p7+/p8 SPRs cleanup, Alexander Graf <=

Prev by Date: Re: [Qemu-ppc] [PATCH 2/2] ppc-e500: implement PCI INTx routing
Next by Date: Re: [Qemu-ppc] [PATCH -V7 3/3] target-ppc: Fix page table lookup with kvm enabled
Previous by thread: [Qemu-ppc] [PATCH 4/5] target-ppc: remove embedded MMU SPRs from 970, P5+/7/7+/8
Next by thread: [Qemu-ppc] [PATCH 0/2] ppc-e500: Adding pci-pin to irq callback and some cleanup
Index(es):
- Date
- Thread