[Top][All Lists]

[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

[Qemu-ppc] [V3 PATCH 0/9] target-ppc: Base ISA V2.07 for Power8

From: Tom Musta
Subject: [Qemu-ppc] [V3 PATCH 0/9] target-ppc: Base ISA V2.07 for Power8
Date: Mon, 10 Feb 2014 11:26:52 -0600

This patch series adds the branch and integer instructions that were 
introduced in Power ISA 2.07.  Specifically,

  - There is a new conditional Branch to Address Register (bctar) instruction.
  - The load/store quadword instructions are now supported in user mode (Book 
  - Quadword atomic instructions have been added (lqarx, stqcx.).

ISA 2.07 additions for other categories (VSX, Altivec, Decimal Floating Point,
transactional memory) are not included in this patch series; they will be 
contributed via other patches.

V2: Addressing review comments from Alex Graf:
    (1) Refactored user-mode and Little Endian checks in the load and store
        quadword instructions.
    (2) Added reserve_val2 element to CPU state in support of quadword atomic

V3: Addressiew review comments from Alex Graf:
    (1) Moved declaration of local variables to the beginning of the block (a la
        C89 standard).
    (2) Fixed bugs in handling of secondary reservation doubleword used in lqarx
        and stqcx. instructions. 

Tom Musta (9):
  target-ppc: Add Flag for bctar
  target-ppc: Add Target Address SPR (TAR) to Power8
  target-ppc: Add bctar Instruction
  target-ppc: Add Flag for ISA 2.07 Load/Store Quadword Instructions
  target-ppc: Add is_user_mode Utility Routine
  target-ppc: Load Quadword
  target-ppc: Store Quadword
  target-ppc: Add Load Quadword and Reserve
  target-ppc: Add Store Quadword Conditional

 linux-user/main.c           |   18 +++++-
 target-ppc/cpu.h            |   10 ++-
 target-ppc/translate.c      |  158 ++++++++++++++++++++++++++++++++++---------
 target-ppc/translate_init.c |   19 +++++-
 4 files changed, 168 insertions(+), 37 deletions(-)

reply via email to

[Prev in Thread] Current Thread [Next in Thread]