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Re: [Qemu-ppc] [PATCH 0/9] target-ppc: Rudimentary Support for Transacti

From: Alexander Graf
Subject: Re: [Qemu-ppc] [PATCH 0/9] target-ppc: Rudimentary Support for Transactional Memory
Date: Thu, 18 Dec 2014 23:52:16 +0100
User-agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.10; rv:31.0) Gecko/20100101 Thunderbird/31.3.0

On 18.12.14 17:34, Tom Musta wrote:
> This patch series introduces rudimentary support for the Transactional Memory
> (TM) feature of Power ISA V2.07.  In a nutshell, software uses the feature by
> initiating a transaction via the tbegin instruction.  Hardware then 
> accumulates
> storage accesses until the transaction is committed via the tend 
> instruction).  
> At this point, either the instruction completes and all storage accesses are 
> atomic with respect to other processors; or the transaction fails and 
> processor
> state reverts to the point of tbegin.  Transaction success or failure is 
> recorded
> in CR[0] and the instruction immediately following tbegin is expected to 
> inspect
> this field and provide an error path to properly handle failure.
> Accurately emulating such a feature in QEMU is quite difficult.  Instead, the
> approach taken here simply fails the transaction at the point of tbegin and
> thus immediately takes software down the error handlling path.  As such, this 
> can
> be considered a toleration mode for any software that utilizes the TM feature.
> Valgrind has taken a similar approach.  There are no immediate plans to 
> implement
> a more sophisticated model.
> Currently, Power8 is the only Power processor that supports TM.

Thanks, applied all to ppc-next.


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