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Re: [Qemu-ppc] [PATCH 2/2] m48t59: add mem_base value to m48t59_init_isa

From: Artyom Tarasenko
Subject: Re: [Qemu-ppc] [PATCH 2/2] m48t59: add mem_base value to m48t59_init_isa()
Date: Mon, 19 Jan 2015 14:12:31 +0100

On Mon, Jan 19, 2015 at 1:59 PM, Paolo Bonzini <address@hidden> wrote:
> On 19/01/2015 13:57, Artyom Tarasenko wrote:
>>> > Is it really ISA if it's MMIO?  In other words, why can't this be a
>>> > sysbus device?
>> On physical machines it's EBus, which is pretty much like 8-bit ISA.
>> So, I think modelling it as ISA is closer to to the reality.
>> But out of curiosity, would it be possible to have a sysbus device
>> somewhere in a middle of PCI space? Do sysbus devices have higher
>> priority if the address spaces overlap? Or do you mean that the PCI
>> controller needs to be modified to have a hole for a sysbus device?
> What does the memory map look like (simplifying to "where can BARs be"
> and "where is the RTC")?

 dev: pbm, id ""
    mmio 000001fe00000000/0000000000010000
    mmio 000001fe01000000/0000000001000000
    mmio 000001fe02000000/0000000000010000
    bus: pci
      dev: ebus, id ""
        addr = 03.0
        class Bridge, addr 00:03.0, pci id 108e:1000 (sub 1af4:1100)
        bar 0: mem at 0x3000000 [0x3ffffff]
        bar 1: i/o at 0x4000 [0x7fff]
        bus: isa.0
          type ISA
          dev: m48t59_isa, id ""
            size = 8192 (0x2000)
            io_base = 8192 (0x2000)

(actually it should be better to have it at the beginning of the
ISA-space, 0x0, but it is not critical, since QEMU's sun4u machine
doesn't exactly match any known physical sun4u machine)


Artyom Tarasenko

SPARC and PPC PReP under qemu blog: http://tyom.blogspot.com/search/label/qemu

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