[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-ppc] [PULL 44/66] ppc: load/store multiple and string insns don't
From: |
David Gibson |
Subject: |
[Qemu-ppc] [PULL 44/66] ppc: load/store multiple and string insns don't do LE |
Date: |
Tue, 6 Sep 2016 13:40:31 +1000 |
From: Benjamin Herrenschmidt <address@hidden>
Just generate an alignment interrupt
Signed-off-by: Benjamin Herrenschmidt <address@hidden>
Signed-off-by: David Gibson <address@hidden>
---
target-ppc/translate.c | 29 +++++++++++++++++++++++++++++
1 file changed, 29 insertions(+)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 1315656..379d3d4 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -2889,6 +2889,11 @@ static void gen_lmw(DisasContext *ctx)
{
TCGv t0;
TCGv_i32 t1;
+
+ if (ctx->le_mode) {
+ gen_align_no_le(ctx);
+ return;
+ }
gen_set_access_type(ctx, ACCESS_INT);
t0 = tcg_temp_new();
t1 = tcg_const_i32(rD(ctx->opcode));
@@ -2903,6 +2908,11 @@ static void gen_stmw(DisasContext *ctx)
{
TCGv t0;
TCGv_i32 t1;
+
+ if (ctx->le_mode) {
+ gen_align_no_le(ctx);
+ return;
+ }
gen_set_access_type(ctx, ACCESS_INT);
t0 = tcg_temp_new();
t1 = tcg_const_i32(rS(ctx->opcode));
@@ -2929,6 +2939,10 @@ static void gen_lswi(DisasContext *ctx)
int ra = rA(ctx->opcode);
int nr;
+ if (ctx->le_mode) {
+ gen_align_no_le(ctx);
+ return;
+ }
if (nb == 0)
nb = 32;
nr = (nb + 3) / 4;
@@ -2952,6 +2966,11 @@ static void gen_lswx(DisasContext *ctx)
{
TCGv t0;
TCGv_i32 t1, t2, t3;
+
+ if (ctx->le_mode) {
+ gen_align_no_le(ctx);
+ return;
+ }
gen_set_access_type(ctx, ACCESS_INT);
t0 = tcg_temp_new();
gen_addr_reg_index(ctx, t0);
@@ -2971,6 +2990,11 @@ static void gen_stswi(DisasContext *ctx)
TCGv t0;
TCGv_i32 t1, t2;
int nb = NB(ctx->opcode);
+
+ if (ctx->le_mode) {
+ gen_align_no_le(ctx);
+ return;
+ }
gen_set_access_type(ctx, ACCESS_INT);
t0 = tcg_temp_new();
gen_addr_register(ctx, t0);
@@ -2989,6 +3013,11 @@ static void gen_stswx(DisasContext *ctx)
{
TCGv t0;
TCGv_i32 t1, t2;
+
+ if (ctx->le_mode) {
+ gen_align_no_le(ctx);
+ return;
+ }
gen_set_access_type(ctx, ACCESS_INT);
t0 = tcg_temp_new();
gen_addr_reg_index(ctx, t0);
--
2.7.4
- [Qemu-ppc] [PULL 24/66] ppc: Make float_check_status() pass the return address, (continued)
- [Qemu-ppc] [PULL 24/66] ppc: Make float_check_status() pass the return address, David Gibson, 2016/09/05
- [Qemu-ppc] [PULL 28/66] ppc: Don't update NIP in lmw/stmw/icbi, David Gibson, 2016/09/05
- [Qemu-ppc] [PULL 36/66] ppc: Don't update NIP if not taking alignment exceptions, David Gibson, 2016/09/05
- [Qemu-ppc] [PULL 32/66] ppc: Don't update NIP in DCR access routines, David Gibson, 2016/09/05
- [Qemu-ppc] [PULL 33/66] ppc: Don't update NIP in facility unavailable interrupts, David Gibson, 2016/09/05
- [Qemu-ppc] [PULL 37/66] ppc: Don't update NIP in dcbz and lscbx, David Gibson, 2016/09/05
- [Qemu-ppc] [PULL 52/66] target-ppc: add vsrv instruction, David Gibson, 2016/09/05
- [Qemu-ppc] [PULL 46/66] target-ppc: implement branch-less divw[o][.], David Gibson, 2016/09/05
- [Qemu-ppc] [PULL 43/66] ppc: Use a helper to generate "LE unsupported" alignment interrupts, David Gibson, 2016/09/05
- [Qemu-ppc] [PULL 58/66] ppc: Fix catching some segfaults in user mode, David Gibson, 2016/09/05
- [Qemu-ppc] [PULL 44/66] ppc: load/store multiple and string insns don't do LE,
David Gibson <=
- [Qemu-ppc] [PULL 39/66] ppc: Handle unconditional (always/never) traps at translation time, David Gibson, 2016/09/05
- [Qemu-ppc] [PULL 57/66] ppc: Fix macio ESCC legacy mapping, David Gibson, 2016/09/05
- [Qemu-ppc] [PULL 63/66] ppc: Improve a few more helper flags, David Gibson, 2016/09/05
- [Qemu-ppc] [PULL 61/66] ppc: Improve flags for helpers loading/writing the time facilities, David Gibson, 2016/09/05
- [Qemu-ppc] [PULL 62/66] ppc: Improve the exception helpers flags, David Gibson, 2016/09/05
- [Qemu-ppc] [PULL 60/66] ppc: Don't generate dead code on unconditional branches, David Gibson, 2016/09/05
- [Qemu-ppc] [PULL 65/66] tests: Resort check-qtest entries in Makefile.include, David Gibson, 2016/09/05
- [Qemu-ppc] [PULL 19/66] ppc: Move DFP ops out of translate.c, David Gibson, 2016/09/05
- [Qemu-ppc] [PULL 66/66] tests: Check serial output of firmware boot of some machines, David Gibson, 2016/09/05
- [Qemu-ppc] [PULL 50/66] target-ppc: add vcmpnez[b, h, w][.] instructions, David Gibson, 2016/09/05